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A reliable PUF in a dual function SRAM

A reliable PUF in a dual function SRAM
A reliable PUF in a dual function SRAM
The Internet of Things (IoTs) employs resource-constrained sensor nodes for sensing and processing data that require robust, lightweight cryptographic primitives. The SRAM Physical Unclonable Function (SRAM-PUF) is a potential candidate for secure key generation. An SRAM-PUF is able to generate random and unique cryptographic keys based on start-up values by exploiting intrinsic manufacturing process variations. The reuse of the available on-chip SRAM memory in a system as a PUF might achieve useful cost efficiency. However, as CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) becomes more pronounced resulting in asymmetric degradation of memory bit cells after prolonged storage of the same bit values. This causes unreliable start-up values for an SRAM-PUF. In this paper, the on-chip memory in the ARM architecture has been used as a case study to investigate reliability in an SRAM-PUF. We show that the bit probability in a 32-bit ARM instruction cache has a predictable pattern and hence predictable aging. Therefore, we propose using an instruction cache as a PUF to save silicon area. Furthermore, we propose a bit selection technique to mitigate the NBTI effect. We show that this technique can reduce the predicted bit error in an SRAM-PUF from 14.18% to 5.58% over 5 years. Consequently, as the bit error reduces, the area overhead of the error-correction circuitry is about 6x smaller compared to that without a bit selection technique.
0167-9260
12-21
Mispan, Mohd Syafiq
568c91c3-c200-441c-887b-8f299635b94e
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Mispan, Mohd Syafiq
568c91c3-c200-441c-887b-8f299635b94e
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Mispan, Mohd Syafiq, Duan, Shengyu, Halak, Basel and Zwolinski, Mark (2019) A reliable PUF in a dual function SRAM. Integration the VLSI Journal, 68, 12-21. (doi:10.1016/j.vlsi.2019.06.001).

Record type: Article

Abstract

The Internet of Things (IoTs) employs resource-constrained sensor nodes for sensing and processing data that require robust, lightweight cryptographic primitives. The SRAM Physical Unclonable Function (SRAM-PUF) is a potential candidate for secure key generation. An SRAM-PUF is able to generate random and unique cryptographic keys based on start-up values by exploiting intrinsic manufacturing process variations. The reuse of the available on-chip SRAM memory in a system as a PUF might achieve useful cost efficiency. However, as CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) becomes more pronounced resulting in asymmetric degradation of memory bit cells after prolonged storage of the same bit values. This causes unreliable start-up values for an SRAM-PUF. In this paper, the on-chip memory in the ARM architecture has been used as a case study to investigate reliability in an SRAM-PUF. We show that the bit probability in a 32-bit ARM instruction cache has a predictable pattern and hence predictable aging. Therefore, we propose using an instruction cache as a PUF to save silicon area. Furthermore, we propose a bit selection technique to mitigate the NBTI effect. We show that this technique can reduce the predicted bit error in an SRAM-PUF from 14.18% to 5.58% over 5 years. Consequently, as the bit error reduces, the area overhead of the error-correction circuitry is about 6x smaller compared to that without a bit selection technique.

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More information

Accepted/In Press date: 2 June 2019
e-pub ahead of print date: 5 June 2019
Published date: September 2019

Identifiers

Local EPrints ID: 431754
URI: https://eprints.soton.ac.uk/id/eprint/431754
ISSN: 0167-9260
PURE UUID: 9c96d6d4-deaf-4f77-849e-f2275e16c657
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 14 Jun 2019 16:30
Last modified: 03 Sep 2019 00:40

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