ACDC: An accuracy- and congestion-aware dynamic traffic control method for networks-on-chip
ACDC: An accuracy- and congestion-aware dynamic traffic control method for networks-on-chip
Many applications exhibit error forgiving features. For these applications, approximate computing provides the opportunity of accelerating the execution time or reducing power consumption, by mitigating computation effort to get an approximate result. Among the components on a chip, network-on-chip (NoC) contributes a large portion to system power and performance. In this paper, we exploit the opportunity of aggressively reducing network congestion and latency by selectively dropping data. Essentially, the importance of the dropped data is measured based on a quality model. An optimization problem is formulated to minimize the network congestion with constraint of the result quality. A lightweight online algorithm is proposed to solve this problem. Experiments show that on average, our proposed method can reduce the execution time by as much as 12.87% and energy consumption by 12.42% under strict quality requirement, speed up execution by 19.59% and reduce energy consumption by 21.20% under relaxed requirement, compared to a recent work on approximate computing approach for NoCs.
approximate computing, many-core system, on-chip network
630-633
Xiao, Siyuan
1f5051df-6bd8-4982-a077-bf8080faf06f
Wang, Xiaohang
95ffd2f0-3e1f-4cbe-8067-b600d6a08f75
Palesi, Maurizio
d4bf02e9-1e72-4b10-8461-2d0088c8cfe0
Singh, Amit Kumar
bb67d43e-34d9-4b58-9295-8b5458270408
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
16 May 2019
Xiao, Siyuan
1f5051df-6bd8-4982-a077-bf8080faf06f
Wang, Xiaohang
95ffd2f0-3e1f-4cbe-8067-b600d6a08f75
Palesi, Maurizio
d4bf02e9-1e72-4b10-8461-2d0088c8cfe0
Singh, Amit Kumar
bb67d43e-34d9-4b58-9295-8b5458270408
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Xiao, Siyuan, Wang, Xiaohang, Palesi, Maurizio, Singh, Amit Kumar and Mak, Terrence
(2019)
ACDC: An accuracy- and congestion-aware dynamic traffic control method for networks-on-chip.
In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).
IEEE.
.
(doi:10.23919/DATE.2019.8715189).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Many applications exhibit error forgiving features. For these applications, approximate computing provides the opportunity of accelerating the execution time or reducing power consumption, by mitigating computation effort to get an approximate result. Among the components on a chip, network-on-chip (NoC) contributes a large portion to system power and performance. In this paper, we exploit the opportunity of aggressively reducing network congestion and latency by selectively dropping data. Essentially, the importance of the dropped data is measured based on a quality model. An optimization problem is formulated to minimize the network congestion with constraint of the result quality. A lightweight online algorithm is proposed to solve this problem. Experiments show that on average, our proposed method can reduce the execution time by as much as 12.87% and energy consumption by 12.42% under strict quality requirement, speed up execution by 19.59% and reduce energy consumption by 21.20% under relaxed requirement, compared to a recent work on approximate computing approach for NoCs.
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More information
e-pub ahead of print date: March 2019
Published date: 16 May 2019
Venue - Dates:
22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, , Florence, Italy, 2019-03-25 - 2019-03-29
Keywords:
approximate computing, many-core system, on-chip network
Identifiers
Local EPrints ID: 431805
URI: http://eprints.soton.ac.uk/id/eprint/431805
ISSN: 1558-1101
PURE UUID: d27ff9c9-8f82-462b-9c46-10369a8fad4a
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Date deposited: 18 Jun 2019 16:30
Last modified: 17 Mar 2024 12:28
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Contributors
Author:
Siyuan Xiao
Author:
Xiaohang Wang
Author:
Maurizio Palesi
Author:
Amit Kumar Singh
Author:
Terrence Mak
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