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An efficient numerical solution technique for VLSI interconnect equations on many-core processors

An efficient numerical solution technique for VLSI interconnect equations on many-core processors
An efficient numerical solution technique for VLSI interconnect equations on many-core processors

This paper presents a technique to accelerate transient simulations of analog circuits using an explicit integration method parallelised on a many-core computer. Usual methods used by SPICE-type simulators are based on Newton-Raphson iterations, which are reliable and numerically stable, but require long CPU processing times. However, although the integration time step in explicit methods is smaller than that used in implicit methods, this technique avoids the calculation of time-consuming computations due to the Jacobian matrix inversion. The proposed method uses an explicit integration scheme based on the fourth order Adams-Bashforth formula. The algorithm has been parallelised on a NVIDIA general purpose GPU using the CUDA programming model. As a case study, the RC ladder model of a VLSI interconnect is simulated on a general purpose graphic processing unit and the achieved performance is then evaluated against that of a multiprocessor CPU. The results show that the proposed technique achieves a speedup of one order of magnitude in comparison with implicit integration techniques executed on a CPU.

GPU, Simulation acceleration, State-space technique, VLSI interconnect
Institute of Electrical and Electronics Engineers Inc.
Doménech-Asensi, Ginés
31bbc5b3-d1d7-4db8-ac37-28f64b8c6735
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Doménech-Asensi, Ginés
31bbc5b3-d1d7-4db8-ac37-28f64b8c6735
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a

Doménech-Asensi, Ginés and Kazmierski, Tom J. (2019) An efficient numerical solution technique for VLSI interconnect equations on many-core processors. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. vol. 2019-May, Institute of Electrical and Electronics Engineers Inc.. (doi:10.1109/ISCAS.2019.8702085).

Record type: Conference or Workshop Item (Paper)

Abstract

This paper presents a technique to accelerate transient simulations of analog circuits using an explicit integration method parallelised on a many-core computer. Usual methods used by SPICE-type simulators are based on Newton-Raphson iterations, which are reliable and numerically stable, but require long CPU processing times. However, although the integration time step in explicit methods is smaller than that used in implicit methods, this technique avoids the calculation of time-consuming computations due to the Jacobian matrix inversion. The proposed method uses an explicit integration scheme based on the fourth order Adams-Bashforth formula. The algorithm has been parallelised on a NVIDIA general purpose GPU using the CUDA programming model. As a case study, the RC ladder model of a VLSI interconnect is simulated on a general purpose graphic processing unit and the achieved performance is then evaluated against that of a multiprocessor CPU. The results show that the proposed technique achieves a speedup of one order of magnitude in comparison with implicit integration techniques executed on a CPU.

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More information

Published date: 1 May 2019
Venue - Dates: 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 2019-05-26 - 2019-05-29
Keywords: GPU, Simulation acceleration, State-space technique, VLSI interconnect

Identifiers

Local EPrints ID: 431877
URI: https://eprints.soton.ac.uk/id/eprint/431877
PURE UUID: 84e9409e-bbc1-4ac0-b1fe-b709da60c52d

Catalogue record

Date deposited: 20 Jun 2019 16:30
Last modified: 20 Jun 2019 16:30

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Contributors

Author: Ginés Doménech-Asensi
Author: Tom J. Kazmierski

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