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Bias temperature instability ageing-resilient digital system design

Bias temperature instability ageing-resilient digital system design
Bias temperature instability ageing-resilient digital system design
CMOS downsizing has posed a growing concern about circuit lifetime reliability. Bias Temperature Instability (BTI) is considered to be a major source of transistor ageing, causing a threshold voltage increase on CMOS devices and affecting circuit performance. In this work, the failure mechanisms caused by BTI effects are investigated and the BTI mitigation methods for multiple CMOS devices in digital systems, including logic circuits and SRAM caches, are presented.

For logic circuits, BTI-induced threshold voltage shift increases the signal arrival time, eventually causing timing violations. The amount of degradation is dependent on the circuit workload. Thus, a statistical method is proposed to capture the degradation range considering different input data, which is useful to predict the BTI degradation on a circuit with unpredictable workloads. Ageing mitigation approaches that can be incorporated in a standard synthesis process are then presented. Specifically, a logic-level method is proposed to restructure logic expressions and reduce BTI stress duty cycle. The logic structure is validated by a mapping strategy. A gate-level optimization method is then presented to further improve the lifetime. The results show our approaches can realize 75.48% lifetime improvement with 1.14% area overhead.

For SRAM devices, unbalanced BTI degradations on the cross-coupled inverters result in a reduction of the static noise margin (SNM), leading to unreliable read operations. The degradation of an SRAM cache can be predicted based on the signal probability of each cell. From the observations of instruction caches, the BTI stress for each cache line generally has similar but unbalanced patterns even when running very different programs. For data caches, the BTI degradations are application dependent, and are thereby unpredictable. Thus, the lifetime of an instruction cache can be improved by periodically flipping each cell to balance the degradation rate. A bit flipping mechanism, called staggered bit flipping (SBF), is proposed. It flips one block a time staggered throughout multiple times to refresh the entire cache array, so that the interruption is minimized. The proposed design fully equalizes BTI stress on all bit positions, and realizes an up to 125% lifetime improvement with negligible timing and area overheads.
University of Southampton
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Duan, Shengyu (2018) Bias temperature instability ageing-resilient digital system design. University of Southampton, Doctoral Thesis, 169pp.

Record type: Thesis (Doctoral)

Abstract

CMOS downsizing has posed a growing concern about circuit lifetime reliability. Bias Temperature Instability (BTI) is considered to be a major source of transistor ageing, causing a threshold voltage increase on CMOS devices and affecting circuit performance. In this work, the failure mechanisms caused by BTI effects are investigated and the BTI mitigation methods for multiple CMOS devices in digital systems, including logic circuits and SRAM caches, are presented.

For logic circuits, BTI-induced threshold voltage shift increases the signal arrival time, eventually causing timing violations. The amount of degradation is dependent on the circuit workload. Thus, a statistical method is proposed to capture the degradation range considering different input data, which is useful to predict the BTI degradation on a circuit with unpredictable workloads. Ageing mitigation approaches that can be incorporated in a standard synthesis process are then presented. Specifically, a logic-level method is proposed to restructure logic expressions and reduce BTI stress duty cycle. The logic structure is validated by a mapping strategy. A gate-level optimization method is then presented to further improve the lifetime. The results show our approaches can realize 75.48% lifetime improvement with 1.14% area overhead.

For SRAM devices, unbalanced BTI degradations on the cross-coupled inverters result in a reduction of the static noise margin (SNM), leading to unreliable read operations. The degradation of an SRAM cache can be predicted based on the signal probability of each cell. From the observations of instruction caches, the BTI stress for each cache line generally has similar but unbalanced patterns even when running very different programs. For data caches, the BTI degradations are application dependent, and are thereby unpredictable. Thus, the lifetime of an instruction cache can be improved by periodically flipping each cell to balance the degradation rate. A bit flipping mechanism, called staggered bit flipping (SBF), is proposed. It flips one block a time staggered throughout multiple times to refresh the entire cache array, so that the interruption is minimized. The proposed design fully equalizes BTI stress on all bit positions, and realizes an up to 125% lifetime improvement with negligible timing and area overheads.

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Published date: December 2018

Identifiers

Local EPrints ID: 433548
URI: http://eprints.soton.ac.uk/id/eprint/433548
PURE UUID: 14d23ab4-f9fc-4881-a080-d518b0aaca37
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 27 Aug 2019 16:30
Last modified: 28 Aug 2019 00:38

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