READ ME File For 'Dataset for: Efficient State Retention in Transiently Powered Computing Systems' Dataset DOI: 10.5258/SOTON/D1071 ReadMe Author: Theodoros D. Verykios, University of Southampton This dataset supports the thesis entitled "Efficient State Retention in Transiently Powered Computing Systems". AWARDED BY: Univeristy of Southampton DATE OF AWARD: 2019 DESCRIPTION OF THE DATA Modelled and experimental data obtained throughout the duration of the PhD on "Efficient State Retention in Transiently Powered Computing Systems". Experimental data mainly obtained from two experimental boards: MSP430FR5739 and LPC-Xpresso 810. Modelled data are an output of ModelSim and Design Compiler. This dataset contains: Date of collection: Setember 2015 - January 2019 Information about geographic location of data collection: Southampton, UK Licence: CC BY 4.0 Related projects/Funders: This work was supported in part by the UK Engineering and Physical Sciences Research Council (EPSRC) under Platform Grant EP/P010164/1 and the PRiME Programme Grant EP/K034448/1. Related publication: Verykios, Theodoros D., Balsamo, Domenico and Merrett, Geoff V. (2018) Selective policies for efficient state retention in transiently-powered embedded systems: exploiting properties of NVM technologies. Sustainable Computing: Informatics and Systems. Tab 1: Figure 3.1: Modelled energy requirement for saving/restoring the system state using the Allocated State policy, applied to a system featuring NVM without erase cost (equation 3.4), using typical parameters of FRAM. Tab 2: Figure 3.2: Modelled energy requirement for saving and restoring the system state using the Allocated State policy, applied to a system featuring NVM with erase cost, using typical parameters of Flash. Tab 3: Figure 3.3: Time and energy overhead of Allocated State on FRAM/Flash-based systems. Tab 4: Figure 3.5: Modelled energy requirement for saving the system state using the Multiple Allocated State Images policy, applied to a system featuring NVM with erase cost (equation 3.7), using typical parameters of Flash. Tab 5: Figure 3.7: Modelled energy requirement for saving the system state using the Updated Blocks policy, applied to a system featuring an asymmetric NVM without erase cost (equation 3.9), using typical parameters of PCM. Tab 6: Figure 3.9: Modelled energy consumption for saving the system state using the Multiple Updated Blocks policy, applied to a system featuring an asymmetric NVM with erase cost (Equation 11), using typical parameters of Flash from Table 2. Tab 7: Figure 3.12: Experimental results showing the energy required to save the system state, when using the Allocated State policy on FRAM. Tab 8: Figure 3.13: Experimental results showing the energy required to save the system state, when using the Allocated State policy on Flash memory. Tab 9: Figure 3.14: Experimental results showing (a) the energy required to save the system state and (b), the number of iterations, when using the Multiple Allocated State Images policy on Flash memory. Tab 10: Figure 3.15: Experimental results showing the restore energy against the number of stored images in NVM, when using the Multiple Allocated State Images policy on Flash memory. Tab 11: Figure 3.16: Experimental results showing (a) the energy required to save the system state and (b) the number of iterations, when using the Multiple Updated Blocks policy on Flash memory. Tab 12: Figure 3.17: Experimental results showing the energy required to save the system state, when using the Updated Blocks policy on asymmetric NVM without erase cost. Policy validated using the available hardware as a proof of concept (Flash, negating erase cost). Tab 13: Figure 3.18: Experimental results showing the average energy required to save each block against percentage of memory contiguously changed. Policy validated using the available hardware as a proof of concept (Flash, negating erase cost). Tab 14: Figure 3.19: Experimental results showing the energy required to save the system state, when using the Allocated State policy on asymmetric NVM without erase cost. Policy validated using the available hardware as a proof of concept (Flash, negating erase cost). Tab 15: Figure 4.1: Usable energy stored in the capacitor (10-20uF) for different hibernation threshold and minimum operating voltages, targeted at FRAM-based systems. Tab 16: Figure 4.2: Usable energy stored in the capacitor (100-200uF) for different hibernation threshold and minimum operating voltages, targeted at FRAM-based systems. Tab 17: Figure 4.9: Effect of different granularity settings on the amount of redundant write operations. Tab 18: Figure 4.10: Dynamic hibernation threshold voltage (VH) adjustment example for an FRAM-based system. Tab 19: Figure 4.11: Effect of different interruption frequencies and hibernation threshold voltages (VH) on the active computation time (tactive), for systems with different capacitance (20uF and 100uF). Tab 20: Figure 5.6: Number of snapshots required to complete each benchmark for various interruption frequencies, using a system featuring FRAM without MeTra. Tab 21: Figure 5.7: Number of snapshots required to complete each benchmark for various interruption frequencies, using a system featuring Flash without MeTra. Tab 22: Figure 5.8: Amount of energy required to complete each benchmark, for various interruption frequencies (fsource), using a system featuring FRAM without the use of MeTra. Tab 23: Figure 5.9: Amount of energy required to complete each benchmark, for various interruption frequencies (fsource), using a system featuring Flash without the use of MeTra. Tab 24: Figure 5.10: Behaviour of MeTra when the FFT benchmark is executed on a system featuring Flash memory, with a source interruption frequency of 2Hz. Tab 25: Figure 5.11: Behaviour of MeTra when the FFT benchmark is executed on a system featuring FRAM memory, with a source interruption frequency of 2Hz. Tab 26: Figure 5.12: Behaviour of MeTra when the FFT benchmark is executed on a system featuring FRAM memory, with a source interruption frequency of 20Hz. Tab 27: Figure 5.13: Minimum active time for each benchmark, for various interruption frequencies (fsource), using a system featuring FRAM with MeTra. Tab 28: Figure 5.14: Minimum active time for each benchmark, for various interruption frequencies (fsource), using a system featuring Flash with MeTra. Tab 29: Figure 5.15: Energy spent on state retention for different benchmarks on system featuring FRAM, with various source interruption frequencies. Tab 30: Figure 5.16: Behaviour of MeTra when the FFT benchmark is executed on a system featuring FRAM memory, with a source interruption frequency of 20Hz, using different granularity settings. Tab 31: Figure 5.17: Hibernation threshold voltage adjustment when the FFT benchmark is executed on a system featuring FRAM memory, with a source interruption frequency of 20Hz, using different granularity settings. Tab 32: Figure 5.18: "Instantaneous" active time when the FFT benchmark is executed on a system featuring FRAM memory, with a source interruption frequency of 20Hz, using different granularity settings. Tab 33: Figure 5.19: Total energy required for saving the system state until the FFT application can be completed, assuming a system featuring FRAM memory, using different granularity settings. University of Southampton, UK