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Performance analysis of high throughput MAP decoder for turbo codes and self concatenated convolutional codes

Performance analysis of high throughput MAP decoder for turbo codes and self concatenated convolutional codes
Performance analysis of high throughput MAP decoder for turbo codes and self concatenated convolutional codes
The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64.
2169-3536
Shaheen, Farzana
a16acee3-efce-4292-8e3e-574ce53d90b0
Butt, Muhammad Fasih Uddin
41f74023-13e7-4203-9580-9017f57217b4
Agha, Shahrukh
3e19434e-c028-45ce-bbf0-f61116ecc469
Ng, Soon
e19a63b0-0f12-4591-ab5f-554820d5f78c
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Shaheen, Farzana
a16acee3-efce-4292-8e3e-574ce53d90b0
Butt, Muhammad Fasih Uddin
41f74023-13e7-4203-9580-9017f57217b4
Agha, Shahrukh
3e19434e-c028-45ce-bbf0-f61116ecc469
Ng, Soon
e19a63b0-0f12-4591-ab5f-554820d5f78c
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c

Shaheen, Farzana, Butt, Muhammad Fasih Uddin, Agha, Shahrukh, Ng, Soon and Maunder, Robert (2019) Performance analysis of high throughput MAP decoder for turbo codes and self concatenated convolutional codes. IEEE Access. (doi:10.1109/ACCESS.2019.2942152).

Record type: Article

Abstract

The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64.

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Performance Analysis of High Throughput MAP Decoder for Turbo Codes and Self Concatenated Convolutional Codes - Proof
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Accepted/In Press date: 8 September 2019
e-pub ahead of print date: 18 September 2019

Identifiers

Local EPrints ID: 434392
URI: http://eprints.soton.ac.uk/id/eprint/434392
ISSN: 2169-3536
PURE UUID: fe013f33-45d7-47e0-9189-4ada855efe55
ORCID for Soon Ng: ORCID iD orcid.org/0000-0002-0930-7194
ORCID for Robert Maunder: ORCID iD orcid.org/0000-0002-7944-2615

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Date deposited: 23 Sep 2019 16:30
Last modified: 07 Oct 2020 05:49

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Contributors

Author: Farzana Shaheen
Author: Muhammad Fasih Uddin Butt
Author: Shahrukh Agha
Author: Soon Ng ORCID iD
Author: Robert Maunder ORCID iD

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