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A spike-latency transceiver with tuneable pulse control for low-energy wireless 3D integration

A spike-latency transceiver with tuneable pulse control for low-energy wireless 3D integration
A spike-latency transceiver with tuneable pulse control for low-energy wireless 3D integration

Wireless 3-D integration using inductive coupling links (ICLs) has recently gained attention as a low-cost alternative to through-silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3-D integration using ICLs is often criticized for its inferior energy efficiency compared with conventional approaches. To address this challenge, in this article, we present a low-energy ICL transceiver that combines a spike-latency encoding scheme (to reduce the number of energy-expensive analog transmit pulses by encoding data in the time domain) and a tunable current driver (to minimize the transmit energy depending on the given integration scenario). The proposed transceiver is modeled mathematically, simulated in 0.35- μ m, 65-nm, and 28-nm CMOS technologies and experimentally validated in a two-tier 3-D stacked silicon test chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4 pJ/bit, representing a reduction >13% when compared with previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). The simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a 7.7× improvement in energy per bit compared with the state-of-the-art implementations across the same communication distance, marking an important progression toward cost and energy-efficient 3-D integration.

3-D integrated circuit (IC), inductive, time-domain coding, transceiver, wireless links
0018-9200
2414-2428
Fletcher, Benjamin James
b9ee2f3f-f125-47df-a73e-e61c0404d4c9
Das, Shidhartha
c1e693af-261c-495d-8f0f-227396df0e3b
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Fletcher, Benjamin James
b9ee2f3f-f125-47df-a73e-e61c0404d4c9
Das, Shidhartha
c1e693af-261c-495d-8f0f-227396df0e3b
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53

Fletcher, Benjamin James, Das, Shidhartha and Mak, Terrence (2020) A spike-latency transceiver with tuneable pulse control for low-energy wireless 3D integration. IEEE Journal of Solid State Circuits, 55 (9), 2414-2428, [9086615]. (doi:10.1109/JSSC.2020.2989543).

Record type: Article

Abstract

Wireless 3-D integration using inductive coupling links (ICLs) has recently gained attention as a low-cost alternative to through-silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3-D integration using ICLs is often criticized for its inferior energy efficiency compared with conventional approaches. To address this challenge, in this article, we present a low-energy ICL transceiver that combines a spike-latency encoding scheme (to reduce the number of energy-expensive analog transmit pulses by encoding data in the time domain) and a tunable current driver (to minimize the transmit energy depending on the given integration scenario). The proposed transceiver is modeled mathematically, simulated in 0.35- μ m, 65-nm, and 28-nm CMOS technologies and experimentally validated in a two-tier 3-D stacked silicon test chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4 pJ/bit, representing a reduction >13% when compared with previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). The simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a 7.7× improvement in energy per bit compared with the state-of-the-art implementations across the same communication distance, marking an important progression toward cost and energy-efficient 3-D integration.

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A Spike-Latency Transceiver with Tuneable Pulse Control for Low-Energy Wireless 3D Integration - Accepted Manuscript
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Accepted/In Press date: 7 April 2020
e-pub ahead of print date: 6 May 2020
Published date: September 2020
Additional Information: Funding Information: Manuscript received December 20, 2019; revised February 16, 2020; accepted April 7, 2020. Date of publication May 6, 2020; date of current version August 26, 2020. This work was supported by the Engineering and Physical Sciences Research Council (EPSRC) under an iCASE award. This article was approved by Guest Editor Jaeha Kim. (Corresponding author: Benjamin J. Fletcher.) Benjamin J. Fletcher is with the Department of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, U.K., and also with ARM Ltd., Cambridge CB1 9NJ, U.K. (e-mail: bjf1g13@ecs.soton.ac.uk). Publisher Copyright: © 1966-2012 IEEE.
Keywords: 3-D integrated circuit (IC), inductive, time-domain coding, transceiver, wireless links

Identifiers

Local EPrints ID: 441286
URI: http://eprints.soton.ac.uk/id/eprint/441286
ISSN: 0018-9200
PURE UUID: 8041dbb7-45af-47b7-808f-f4d93b70287d
ORCID for Benjamin James Fletcher: ORCID iD orcid.org/0000-0002-4957-1934

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Date deposited: 08 Jun 2020 16:32
Last modified: 22 Jul 2022 23:35

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Contributors

Author: Benjamin James Fletcher ORCID iD
Author: Shidhartha Das
Author: Terrence Mak

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