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A 3D-stacked cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 simultaneous wireless inter-tier data and power transfer

A 3D-stacked cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 simultaneous wireless inter-tier data and power transfer
A 3D-stacked cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 simultaneous wireless inter-tier data and power transfer
This paper presents a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus. The proposed design is the first implementation of a wireless link as part of a standard SoC bus, and achieves 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250um channel. This also makes it the smallest ever reported inductive data and power link.
Fletcher, Benjamin James
b9ee2f3f-f125-47df-a73e-e61c0404d4c9
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Das, Shidhartha
c1e693af-261c-495d-8f0f-227396df0e3b
Fletcher, Benjamin James
b9ee2f3f-f125-47df-a73e-e61c0404d4c9
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Das, Shidhartha
c1e693af-261c-495d-8f0f-227396df0e3b

Fletcher, Benjamin James, Mak, Terrence and Das, Shidhartha (2020) A 3D-stacked cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 simultaneous wireless inter-tier data and power transfer. In Proceedings of 2020 IEEE Symposium on VLSI Circuits. (In Press)

Record type: Conference or Workshop Item (Paper)

Abstract

This paper presents a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus. The proposed design is the first implementation of a wireless link as part of a standard SoC bus, and achieves 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250um channel. This also makes it the smallest ever reported inductive data and power link.

Text
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 Simultaneous Wireless Inter-Tier Data and Power Transfer - Accepted Manuscript
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Accepted/In Press date: 1 April 2020
Venue - Dates: 2020 Symposia on VLSI Technology and Circuits, United States, 2020-06-14 - 2020-06-19

Identifiers

Local EPrints ID: 442837
URI: http://eprints.soton.ac.uk/id/eprint/442837
PURE UUID: 6573d25e-a205-4a29-8e68-38a34246eaa4
ORCID for Benjamin James Fletcher: ORCID iD orcid.org/0000-0002-4957-1934

Catalogue record

Date deposited: 28 Jul 2020 16:41
Last modified: 07 Oct 2020 04:53

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Contributors

Author: Benjamin James Fletcher ORCID iD
Author: Terrence Mak
Author: Shidhartha Das

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