READ ME File For 'Dataset for: High bandwidth capacitance efficient Silicon MOS modulator'

Dataset DOI: https://doi.org/10.5258/SOTON/D1257

ReadMe Author: Weiwei Zhang, University of Southampton [OPTIONAL add ORCID ID]

This dataset supports the publication:
AUTHORS: Weiwei Zhang, Kapil Debnath, Bigeng Chen, Ke Li, Shenghao Liu, Martin Ebert, Jamie Dean Reynolds, Ali Z. Khokhar, Callum Littlejohns, James Byers, Muhammad K. Husain, Frederic Y. Gardes, Shinichi Saito, David J. Thomson
TITLE: High bandwidth capacitance efficient Silicon MOS modulator

JOURNAL: Journal of Lightwave Technology
PAPER DOI IF KNOWN: DOI: 10.1109/JLT.2020.3026945


This dataset contains:


The figures are as follows:


Fig. 2. Simulated phase changes as function of applied forward bias on HSISCAP phase shifters with (a) TM and (b) TE modes. Calculated phase change efficiencies VπL for TM (c) and TE (d) modes confined in HSISCAP waveguides. V-SISCAP phase shifter performance is compared with H-SISCAP in (a) and (c).

Fig. 3. The simulated capacitance per length is shown in (a) for all discussed SISCAP waveguides in Fig.2. The capacitance efficiency parameters Cπ, Qπ have been compared in (b).

Fig. 4. (a), Schematic of the H-SISCAP phase shifter waveguide cross-section design with tox 40 nm. (b), Fabricated H-SISCAP modulator with phase shifter length 200 µm (c), Cross-section TEM image of fabricated H-SISCAP waveguide. (d), Measured transmission spectra shift as function of applied forward bias for the TM mode.

Fig. 5. (a), Measured null wavelength shift as function of applied forward bias for the TM mode (b), Extracted phase change as function of DC bias.

Fig. 6. (a) & (b), Measured and fitted real and imaginary part of S11 for 200 µm long phase shifter. The fitted parameters in the inset equivalent circuit in (a) are Cp = 9.6fF, Cpad 133 fF, Cmos 70 fF, Rsub 240 ohms, and Rmos 15 ohms. (c) Extracted effective capacitance (Ceff) from measured S11 with bias voltage 0 and 5 V.

Fig. 7. Experimentally measured (a) 30 Gbit/s and (b) 60 Gbit/s eye diagrams without DCA equalization, and (c) 72 Gbit/s eye diagram with 2 taps DCA equalization. The insets are the eye diagrams of input RF signals.

Fig. 8. (a), Comparison between experimental measured ERs and calculated ERs with different V_pp^eff assumptions. (b), ERs of 40 Gbit/s eye diagram versus applied DC bias voltage.

Date of data collection: 04-2019 to 01-2020

Information about geographic location of data collection: Dave Thomson's lab 2052 building 53, University of southampton



Related projects: prosperity partnership (EP/R003076/1), European Commission H2020 PICTURE
Project (780930), EPSRC Standard Grant (EP/M009416/1), EPSRC Manufacturing Fellowship (EP/M008975/1), EPSRC Platform Grant (EP/N013247/1), University of Southampton Zepler Institute Research Collaboration Stimulus Fund, and Hitachi. 

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Date that the file was creat 05-2020