Novel design in mixed-signal and machine learning resilient architecture physical unclonable functions

Abstract

Physical Unclonable Functions (PUFs) are seen as a security primitive that can be embedded in Integrated Circuits (ICs). In recent years, electronic devices have been widely used because of their convenience; in this way, the issue of security becomes more and more critical. PUF technology leverages the inherent properties of integrated circuits to provide a promising solution to security-related problems, especially for lightweight devices. PUFs capture random process changes in devices caused by chip manufacturing and convert them into unique digital keys. However, with the emergence of new attack technologies, there are increasing challenges to chip security. Furthermore, Machine Learning (ML) is the most recent technique that is commonly used to attack PUFs and has a low cost. Therefore, the unclonability property of PUF technology becomes less certain. Besides, the instability of the PUF due to environmental changes has led to additional circuits being used to correct the resulting errors. This thesis studies ML resilience improvement techniques for lightweight authentication devices based on PUF technology. This thesis contributes in three major ways. The first contribution is a technique to construct a new PUF structure using mixed-signal circuits. The simulation results demonstrate that the PUF has better performance in uniformity, uniqueness, and reliability. The second contribution is an architecture for combining different types of PUF structures into a combined system, to give resilience against ML attacks. The technique has been implemented by combing A-PUF, CM-PUF, and DC-PUF in TSMC 65-nm technology. The simulation results show that the predictability is reduced from 99% to about 50% representing good randomness on a DC-DC PUF. Hence, a security system can be built by using this technique of combining other PUFs. The third contribution to the field is that the complexity of a PUF-based system is increased through the design and implementation of a multi-stage architecture on FPGAs, showing improved results against ML attacks. RO-PUF is used as the primary cell to build two-stage and three stage PUF structures. For the three-stage PUF, the experiment shows the predictability is reduced from 99% to around 65%.

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Identifiers

ORCID for Haibo Su: orcid.org/0000-0003-2619-9276

ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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