READ ME file for DATA set for article titled ‘Investigating stability and tunability of quantum dot transport in silicon MOSFETs via the application of electrical stress’

DATASET DOI: https://doi.org/10.5258/SOTON/D1910.

Licence: CC BY

Date of data production: 28/10/2020 - 22/12/2020

READ ME author: Joseph Hillier, ECS, Faculty of Engineering and Physical Sciences, University of Southampton, SO17 1BJ, UK

This dataset supports the publication:
AUTHORS:  J. Hillier, K. Ibukuro, F. Liu, M. K. Husain, J. Byers, H. N. Rutt, I. Tomita, Y. Tsuchiya and S. Saito 
TITLE: ‘Investigating stability and tunability of quantum dot transport in silicon MOSFETs via the application of electrical stress’
JOURNAL: IOP Journal of Physics D: Applied Physics

This dataset contains:
All figures that appear in the publication in the folder “Figures”.
Raw data for measurement for each figure in the folder “Raw_data”.

Figures in the publication (Figure 1, 2, 3, 4 and 5) correspond to the files in the folder “Figures” as follows;

Figure1; Figure1.pdf
Figure2; Figure2.pdf
Figure3; Figure3.pdf
Figure4; Figure4.pdf
Figure5; Figure5.pdf


Figure 1 and Figure 2 consist of diagrams created on Inkscape and PowerPoint as well as experimental data. Figures 3, 4 and 5 were generated based on experimental data. Below are the explanations of how each figure was generated using the raw data.


Figure 1

(a), (b) and (c) were generated via Inkscape. (d) The graph was plotted for line Vsd = 0.5 mV using file: 'Initial -550-750mV stress CSD PLC1 [(2) ; 28_10_2020 00_33_15]'.

Figure 2

(a) was created using 'pMOS_stress_-4.0V_Vg [(1) ; 17_03_2021 19_15_32] by plotting Ig, Isub and Ig-Isub.

(b) Illustration was created using Inkscape.

Figure 3

(a)(i)-(v) Charge stabilitity diagrams were generated by plotting Vsd and Id using the following data:

Initial -550-750mV stress CSD PLC1 [(2) ; 28_10_2020 00_33_15]
-4.0 V -550-750mV stress CSD PLC1 [(1) ; 29_10_2020 00_27_41]
-4.2 V -550-750mV stress CSD PLC1 [(1) ; 29_10_2020 15_43_34]
-4.4 V -550-750mV stress CSD PLC1 [(3) ; 29_10_2020 21_56_34]
-4.6 V-550-750mV stress CSD PLC1 [(4) ; 30_10_2020 12_02_14]

(b)(i)-(v) Charge stabilitity diagrams were generated by plotting Vsd and Id using the following data:

After 1st TC Initial -550-750mV stress CSD PLC1 [(2) ; 12_12_2020 14_09_14]
After 1st TC -4 V-550-750mV stress CSD PLC1 [(2) ; 12_12_2020 14_09_14]
After 1st TC -4.2 V-550-750mV stress CSD PLC1 [(1) ; 12_12_2020 19_36_23]
After 1st TC -4.4 V-550-750mV stress CSD PLC1 [(1) ; 13_12_2020 00_46_05]
After 1st TC -4.6 V-550-750mV stress CSD PLC1 [(1) ; 13_12_2020 06_05_46]

(c)(i)-(v) Charge stabilitity diagrams were generated by plotting Vsd and Id using the following data:

After 2nd TC initial-550-750mV stress CSD PLC1 [(1) ; 17_03_2021 13_27_52]
After 2nd TC -4 V -550-750mV stress CSD PLC1 [(1) ; 17_03_2021 21_43_08]
After 2nd TC -4.2 V -550-750mV stress CSD PLC1 [(1) ; 18_03_2021 00_18_23]
After 2nd TC -4.4 V -550-750mV stress CSD PLC1 [(1) ; 18_03_2021 02_54_11]
After 2nd TC -4.6 V -550-750mV stress CSD PLC1 [(1) ; 18_03_2021 05_29_02]

Figure 4

(a)(i)-(iii) Charge stability diagrams were generated by plotting Vsd and Id using the following data:

After 2nd TC -4.8 V-550-750mV stress CSD PLC1 [(1) ; 18_03_2021 08_06_13]
After 2nd TC -5.0 V-550-750mV stress CSD PLC1 [(1) ; 18_03_2021 10_48_47]
After 2nd TC -5.2 V -550-750mV stress CSD PLC1 [(1) ; 18_03_2021 14_45_59]

(b) Plot generated using 'After 2nd TC -5.2 V -550-750mV stress CSD PLC1 [(1) ; 18_03_2021 14_45_59]' for Vsd = 5, 10, 15, 20 and 25 mV.

(c) Plot generated using data:

After 2nd TC initial-550-750mV stress CSD PLC1 [(1) ; 17_03_2021 13_27_52]
pMOS_stress_-4.0V_Vg [(1) ; 17_03_2021 19_15_32]
pMOS_stress_-4.2V_Vg [(1) ; 17_03_2021 21_50_50]
pMOS_stress_-4.4V_Vg [(1) ; 18_03_2021 00_26_38]
pMOS_stress_-4.6V_Vg [(1) ; 18_03_2021 03_02_20]
pMOS_stress_-4.8V_Vg [(1) ; 18_03_2021 05_38_05]
pMOS_stress_-5.0V_Vg [(1) ; 18_03_2021 08_16_50]
pMOS_stress_-5.2V_Vg [(1) ; 18_03_2021 12_16_09]
pMOS_stress_-5.4V_Vg [(1) ; 18_03_2021 14_53_34]
pMOS_stress_-5.6V_Vg [(1) ; 18_03_2021 17_32_14]

Where the difference in the threshold voltage (greater than 1nA) between each Vg,max and the inital data at Vsd= -10 mV was calculated and plotted for each Vg,max value.

(d) Plot generated using:

pMOS_stress_-4.0V_Vg [(1) ; 17_03_2021 19_15_32]
pMOS_stress_-4.2V_Vg [(1) ; 17_03_2021 21_50_50]
pMOS_stress_-4.4V_Vg [(1) ; 18_03_2021 00_26_38]
pMOS_stress_-4.6V_Vg [(1) ; 18_03_2021 03_02_20]
pMOS_stress_-4.8V_Vg [(1) ; 18_03_2021 05_38_05]
pMOS_stress_-5.0V_Vg [(1) ; 18_03_2021 08_16_50]
pMOS_stress_-5.2V_Vg [(1) ; 18_03_2021 12_16_09]
pMOS_stress_-5.4V_Vg [(1) ; 18_03_2021 14_53_34]
pMOS_stress_-5.6V_Vg [(1) ; 18_03_2021 17_32_14]

Where the average integration time per point (0.175 seconds), together with the surface gate area (10*0.06 um), Ig-Iwell current (electrons) and Iwell (holes) was using in equation (1) in the paper to calculate the total charge fluence for each stress double sweep.

Figure 5

(a)(i) Plot generated using:

pMOS_IdVg HR Arr 10K [(4) ; 20_12_2020 15_01_26]
pMOS_IdVg HR Arr 12K [(5) ; 20_12_2020 15_18_24]
pMOS_IdVg HR Arr 14K [(6) ; 20_12_2020 15_31_12]
pMOS_IdVg HR Arr 16K [(7) ; 20_12_2020 15_44_18]
pMOS_IdVg HR Arr 18K [(8) ; 20_12_2020 15_57_41]
pMOS_IdVg HR Arr 20K [(9) ; 20_12_2020 16_21_47]
pMOS_IdVg HR Arr 25K [(10) ; 20_12_2020 16_35_48]
pMOS_IdVg HR Arr 30K [(11) ; 20_12_2020 16_50_22]
pMOS_IdVg HR Arr 35K [(12) ; 20_12_2020 17_04_51]
pMOS_IdVg HR Arr 40K [(1) ; 20_12_2020 17_20_49]

For Vsd = -5 mV over the Vg range.

(a)(ii) Plot generated using:

pMOS_IdVg HR mArr -4V 10K [(1) ; 21_12_2020 10_45_16]
pMOS_IdVg HR mArr -4V 12K [(2) ; 21_12_2020 10_50_52]
pMOS_IdVg HR mArr -4V 14K [(3) ; 21_12_2020 10_56_15]
pMOS_IdVg HR mArr -4V 16K [(4) ; 21_12_2020 11_02_17]
pMOS_IdVg HR mArr -4V 18K [(5) ; 21_12_2020 11_07_59]
pMOS_IdVg HR mArr -4V 20K [(6) ; 21_12_2020 11_13_07]
pMOS_IdVg HR mArr -4V 25K [(7) ; 21_12_2020 11_22_19]
pMOS_IdVg HR mArr -4V 30K [(8) ; 21_12_2020 11_28_38]
pMOS_IdVg HR mArr -4V 35K [(9) ; 21_12_2020 11_34_49]
pMOS_IdVg HR mArr -4V 40K (2) [(11) ; 21_12_2020 11_45_08]

For Vsd = -5 mV over the Vg range.

(b)(i)-(iii) The above data in (a)(i) was used, where the QD peak Id values corresponding to the labelled quantum dots in Figure 5.(a)(i), together with equation (2) to estimate the activation energy via the gradient in the thermal emission regime at each Vg,max.

(b)(iv)-(vi) The above data in (b)(i) was used, where the QD peak Id values corresponding to the labelled quantum dots in Figure 5.(a)(ii), together with equation (2) to estimate the activation energy via the gradient in the thermal emission regime at each Vg,max.
TABLE I

The QD properties displayed in this table were calculated using Figure 3.(a) by measuring the Coulomb diamond dimensions (for negative Vsd) and estimating the activation energy via the same method as Figure 5. (b)(i)-(vi) using data:

Initial -550-750mV stress CSD PLC1 [(2) ; 28_10_2020 00_33_15]
-4.0 V -550-750mV stress CSD PLC1 [(1) ; 29_10_2020 00_27_41]
-4.2 V -550-750mV stress CSD PLC1 [(1) ; 29_10_2020 15_43_34]
-4.4 V -550-750mV stress CSD PLC1 [(3) ; 29_10_2020 21_56_34]
-4.6 V-550-750mV stress CSD PLC1 [(4) ; 30_10_2020 12_02_14]
pMOS_IdVg HR Arr 10K [(4) ; 20_12_2020 15_01_26]
pMOS_IdVg HR Arr 12K [(5) ; 20_12_2020 15_18_24]
pMOS_IdVg HR Arr 14K [(6) ; 20_12_2020 15_31_12]
pMOS_IdVg HR Arr 16K [(7) ; 20_12_2020 15_44_18]
pMOS_IdVg HR Arr 18K [(8) ; 20_12_2020 15_57_41]
pMOS_IdVg HR Arr 20K [(9) ; 20_12_2020 16_21_47]
pMOS_IdVg HR Arr 25K [(10) ; 20_12_2020 16_35_48]
pMOS_IdVg HR Arr 30K [(11) ; 20_12_2020 16_50_22]
pMOS_IdVg HR Arr 35K [(12) ; 20_12_2020 17_04_51]
pMOS_IdVg HR Arr 40K [(1) ; 20_12_2020 17_20_49]
pMOS_IdVg HR mArr -4V 10K [(1) ; 21_12_2020 10_45_16]
pMOS_IdVg HR mArr -4V 12K [(2) ; 21_12_2020 10_50_52]
pMOS_IdVg HR mArr -4V 14K [(3) ; 21_12_2020 10_56_15]
pMOS_IdVg HR mArr -4V 16K [(4) ; 21_12_2020 11_02_17]
pMOS_IdVg HR mArr -4V 18K [(5) ; 21_12_2020 11_07_59]
pMOS_IdVg HR mArr -4V 20K [(6) ; 21_12_2020 11_13_07]
pMOS_IdVg HR mArr -4V 25K [(7) ; 21_12_2020 11_22_19]
pMOS_IdVg HR mArr -4V 30K [(8) ; 21_12_2020 11_28_38]
pMOS_IdVg HR mArr -4V 35K [(9) ; 21_12_2020 11_34_49]
pMOS_IdVg HR mArr -4V 40K (2) [(11) ; 21_12_2020 11_45_08]
pMOS_IdVg HR mArr -4.2V 10K [(1) ; 21_12_2020 15_26_37]
pMOS_IdVg HR mArr -4.2V 12K [(2) ; 21_12_2020 15_31_43]
pMOS_IdVg HR mArr -4.2V 14K [(3) ; 21_12_2020 15_37_12]
pMOS_IdVg HR mArr -4.2V 16K [(4) ; 21_12_2020 15_42_38]
pMOS_IdVg HR mArr -4.2V 18K [(5) ; 21_12_2020 15_48_24]
pMOS_IdVg HR mArr -4.2V 20K [(6) ; 21_12_2020 15_53_15]
pMOS_IdVg HR mArr -4.2V 25K [(7) ; 21_12_2020 15_59_04]
pMOS_IdVg HR mArr -4.2V 30K [(8) ; 21_12_2020 16_05_10]
pMOS_IdVg HR mArr -4.2V 35K (2) [(10) ; 21_12_2020 16_19_30]
pMOS_IdVg HR mArr -4.2V 40K [(11) ; 21_12_2020 16_29_01]
pMOS_IdVg HR mArr -4.4V 10K [(1) ; 21_12_2020 21_04_52]
pMOS_IdVg HR mArr -4.4V 12K [(2) ; 21_12_2020 21_09_47]
pMOS_IdVg HR mArr -4.4V 14K [(4) ; 21_12_2020 21_20_42]
pMOS_IdVg HR mArr -4.4V 16K [(5) ; 21_12_2020 21_25_32]
pMOS_IdVg HR mArr -4.4V 18K [(6) ; 21_12_2020 21_30_07]
pMOS_IdVg HR mArr -4.4V 20K [(8) ; 21_12_2020 21_38_34]
pMOS_IdVg HR mArr -4.4V 25K [(9) ; 21_12_2020 21_44_33]
pMOS_IdVg HR mArr -4.4V 30K [(10) ; 21_12_2020 21_52_00]
pMOS_IdVg HR mArr -4.4V 35K [(11) ; 21_12_2020 21_58_57]
pMOS_IdVg HR mArr -4.4V 40K [(1) ; 21_12_2020 22_20_24]
pMOS_IdVg HR mArr -4.6V 10K [(1) ; 22_12_2020 11_08_30]
pMOS_IdVg HR mArr -4.6V 12K [(2) ; 22_12_2020 11_16_56]
pMOS_IdVg HR mArr -4.6V 14K [(3) ; 22_12_2020 11_22_30]
pMOS_IdVg HR mArr -4.6V 16K [(4) ; 22_12_2020 11_28_45]
pMOS_IdVg HR mArr -4.6V 18K [(5) ; 22_12_2020 11_35_23]
pMOS_IdVg HR mArr -4.6V 20K [(6) ; 22_12_2020 11_44_07]
pMOS_IdVg HR mArr -4.6V 25K [(8) ; 22_12_2020 11_56_53]
pMOS_IdVg HR mArr -4.6V 30K [(9) ; 22_12_2020 12_03_29]
pMOS_IdVg HR mArr -4.6V 35K [(10) ; 22_12_2020 12_13_28]
pMOS_IdVg HR mArr -4.6V 40K [(11) ; 22_12_2020 12_36_19]