READ ME File For 'Dataset for Experimental Demonstration of RRAM-based Computational Cells for Reconfigurable Mixed-Signal Neuro-Inspired Circuits and Systems' Dataset DOI: https://doi.org/10.5258/SOTON/D2031 ReadMe Author: Georgios Papandroulidakis, University of Southampton ORCID ID This dataset supports the thesis entitled Experimental Demonstration of RRAM-based Computational Cells for Reconfigurable Mixed-Signal Neuro-Inspired Circuits and Systems AWARDED BY: University of Southampton DATE OF AWARD: 2021 DESCRIPTION OF THE DATA [The data was collected between March 2017 and July 2021. Experimental processes involving the use of probe station and bench-top measurement instrumentation was employed for the collection of the experimental data. For the simulations, Cadence's Virtuoso Spectre and LTSpice were used to simulate and gather data of the circuits and systems under test. Processing of the data was performed through use of MATLAB and Python. The data is organised per figure per experiment. Labelling of each separate data file denotes the specific case of simulation or experiment.] This dataset contains: The folder "Characterisation Examples Data" that contains the data used to describe RRAM devices characterisation examples. The folder "Combined MAC-TL Gate Data" that contains the data for the simulation in Cadence's Virtuoso for the combined Multiply-ACcumulate (MAC) and Threshold Logic (TL) gate proposed in this thesis. The folder "MAC Circuit Data" that contains the data for the simulation and experiments of the RRAM-based Multiply-ACumulate (MAC) circuit proposed in this thesis. The folder "TLG Data" that contains the data for the simulations and experiments of the RRAM-based Threshold Logic Gate proposed in this thesis. The folder "WTA Data" that contains the data for the simulation of the Winner Take All system proposed in this thesis. The folder "WUC Data" that contains the data for the simulation of the Wake Up Circuit system proposed in this thesis. Date of data collection: March 2017 - July 2021 Information about geographic location of data collection: Southampton, United Kingdom Licence: Creative Commons Attribution CC-BY Related projects/Funders: Engineering and Physical Sciences Research Council (EPSRC) EP/K017829/1 Related publication: G. Papandroulidakis, A. Serb, A. Khiat, G. V. Merrett and T. Prodromakis, “Practical Implementation of Memristor-Based Threshold Logic Gates”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, August 2019 G. Papandroulidakis, A. Serb, A. Khiat, Geoff V. Merrett and T. Prodromakis, “Prac- tical Implementation of digital in-analogue out memristor-based logic circuit” in Inter- national Conference on Memristive Materials, Devices and Systems (MEMRISYS) 2019, 2019 G. Papandroulidakis, L. Michalas, A. Serb, A. Khiat, Geoff V. Merrett and T. Prodro- makis “A Digital-In-Analogue-Out Logic Gate Based on Metal-Oxide Memristor De- vices”, in IEEE International Symposium on Circuits and Systems (ISCAS) 2019, 2019 A. Serb, G. Papandroulidakis, A. Khiat, and T. Prodromakis, “Plane-Splitting Logic Techniques using Hyrbid CMOS-Memristor Circuits and Systems,” in International Conference on Memristive Materials, Devices and Systems (MEMRISYS) 2018, 2018. G. Papandroulidakis, A. Khiat, A. Serb, S. Stathopoulos, L. Michalas, and T. Pro- dromakis, “Desing and Practical Implementation of Memristor-based Threshold Logic Gate,” in International Conference on Memristive Materials, Devices and Systems (MEM- RISYS) 2018, 2018 A. Serb, G. Papandroulidakis, A. Khiat, and T. Prodromakis, “Processing big-data with Memristive Technologies: Splitting the Hyperplane Efficiently,” in IEEE Interna- tional Symposium on Circuits and Systems (ISCAS) 2018, 2018 G. Papandroulidakis, A. Khiat, A. Serb, S. Stathopoulos, L. Michalas, and T. Pro- dromakis, “Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates,” in IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018 Date that the file was created: November, 2021