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A high-level approach for energy efficiency improvement of FPGAs by voltage trimming

A high-level approach for energy efficiency improvement of FPGAs by voltage trimming
A high-level approach for energy efficiency improvement of FPGAs by voltage trimming
Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This paper proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a 32×32 matrix-matrix multiplication and a simple multi-layer neural network implemented on two Xilinx ZC702 Field-Programmable Gate Array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.
Calibration, Clocks, Delays, Field programmable gate arrays, Tools, Voltage, Voltage control, deep neural networks., high level synthesis, low power, low voltage, matrix multiplier
0278-0070
Safarpour, Mehdi
7b3df67d-f0dc-4310-8496-b1ceaeb76309
Xun, Lei
51a0da82-6979-49a8-8eff-ada011f5aff5
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Silven, Olli
706f2edf-51ad-4922-8973-0afa3adc09ee
Safarpour, Mehdi
7b3df67d-f0dc-4310-8496-b1ceaeb76309
Xun, Lei
51a0da82-6979-49a8-8eff-ada011f5aff5
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Silven, Olli
706f2edf-51ad-4922-8973-0afa3adc09ee

Safarpour, Mehdi, Xun, Lei, Merrett, Geoff and Silven, Olli (2021) A high-level approach for energy efficiency improvement of FPGAs by voltage trimming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (doi:10.1109/TCAD.2021.3127153).

Record type: Article

Abstract

Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This paper proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a 32×32 matrix-matrix multiplication and a simple multi-layer neural network implemented on two Xilinx ZC702 Field-Programmable Gate Array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.

Text
A High-Level Approach for Energy EfficiencyImprovement of FPGAs by Voltage Trimming - Accepted Manuscript
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More information

Accepted/In Press date: 8 November 2021
Published date: 13 November 2021
Keywords: Calibration, Clocks, Delays, Field programmable gate arrays, Tools, Voltage, Voltage control, deep neural networks., high level synthesis, low power, low voltage, matrix multiplier

Identifiers

Local EPrints ID: 453284
URI: http://eprints.soton.ac.uk/id/eprint/453284
ISSN: 0278-0070
PURE UUID: bfcdb7c7-845d-4b04-a889-ad51d0e69ac6
ORCID for Geoff Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 12 Jan 2022 17:31
Last modified: 18 Jan 2022 02:38

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Contributors

Author: Mehdi Safarpour
Author: Lei Xun
Author: Geoff Merrett ORCID iD
Author: Olli Silven

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