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Impact of adiabatic logic families on the power-clock generator energy efficiency

Impact of adiabatic logic families on the power-clock generator energy efficiency
Impact of adiabatic logic families on the power-clock generator energy efficiency
Due to the low-power requirement by devices deployed in Near Field Communication (NFC) application operating at low frequencies, adiabatic logic is a good candidate for their implementation and can be used to reduce energy consumption. Adiabatic logic works using an AC power-clock supply. However, generating the AC power-clock increases the energy consumption of the complete adiabatic system. A lot of work has been done on generating the AC power-clocks using resonant circuits and a handful by using the stepwise capacitor based circuit. But the literature lacks the study of the impact of adiabatic logic families’ on the power-clock generator energy dissipation and efficiency. In this paper, we investigate the effect of adiabatic logic families working with 4-phase power-clock generators designed using a 2-StepWise Charging (SWC) circuit. The analysis of the energy dissipation for single power-clock is done taking into account the parasitic resistance and capacitance of the adiabatic logic and power-clock network. Experiments based on simulation results show that the adiabatic logic families’ impacts both the energy consumption and efficiency of the complete adiabatic system.
25-28
Maheshwari, Sachin
f09ac1de-0e3d-410d-a7e2-f4d54a1459b9
Kale, Izzet
c95f4beb-432b-4fed-b464-18a4c2e641cf
Maheshwari, Sachin
f09ac1de-0e3d-410d-a7e2-f4d54a1459b9
Kale, Izzet
c95f4beb-432b-4fed-b464-18a4c2e641cf

Maheshwari, Sachin and Kale, Izzet (2019) Impact of adiabatic logic families on the power-clock generator energy efficiency. In 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). pp. 25-28 .

Record type: Conference or Workshop Item (Paper)

Abstract

Due to the low-power requirement by devices deployed in Near Field Communication (NFC) application operating at low frequencies, adiabatic logic is a good candidate for their implementation and can be used to reduce energy consumption. Adiabatic logic works using an AC power-clock supply. However, generating the AC power-clock increases the energy consumption of the complete adiabatic system. A lot of work has been done on generating the AC power-clocks using resonant circuits and a handful by using the stepwise capacitor based circuit. But the literature lacks the study of the impact of adiabatic logic families’ on the power-clock generator energy dissipation and efficiency. In this paper, we investigate the effect of adiabatic logic families working with 4-phase power-clock generators designed using a 2-StepWise Charging (SWC) circuit. The analysis of the energy dissipation for single power-clock is done taking into account the parasitic resistance and capacitance of the adiabatic logic and power-clock network. Experiments based on simulation results show that the adiabatic logic families’ impacts both the energy consumption and efficiency of the complete adiabatic system.

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Published date: 2019

Identifiers

Local EPrints ID: 453364
URI: http://eprints.soton.ac.uk/id/eprint/453364
PURE UUID: 8b2fe157-fe97-4290-8b82-d826e5cf8f9d

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Date deposited: 13 Jan 2022 18:15
Last modified: 13 Jan 2022 18:15

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Contributors

Author: Sachin Maheshwari
Author: Izzet Kale

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