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Templatised soft floating-point for high-level synthesis

Templatised soft floating-point for high-level synthesis
Templatised soft floating-point for high-level synthesis

High-level Synthesis (HLS) tools have greatly increased the productivity of FPGA application development, making it possible to easily create highly-parallel application-Accelerators. However, while FPGAs are known for the ability to customise the number representation of data-paths, most HLS work only uses custom-precision for fixed-point representations, and for floating-point relies on the 64-, 32-, and 16-bitformats provided by vendors. This paper presents a solution for parametrised floating-point in HLS via C++ templates, allowing for compile-Time selection of exponent and fraction widths, including the use of mixed precisions for input arguments and result types. By using arbitrary width integers and compile-Time logic the resulting operators describe the same data-path as an external floating-point IP generator, while still allowing the HLS tool to perform detailed optimisation and scheduling of the internal components. We show that the resulting custom-width HLS cores provide similar area and performance to platform-native vendor IP blocks, while adding full support for heterogeneous precision floating-point data-paths to HLS tools.

custom precision, Floating point, high level synthesis, template hls
227-235
Institute of Electrical and Electronics Engineers Inc.
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c

Thomas, David B. (2019) Templatised soft floating-point for high-level synthesis. In Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019. Institute of Electrical and Electronics Engineers Inc. pp. 227-235 . (doi:10.1109/FCCM.2019.00038).

Record type: Conference or Workshop Item (Paper)

Abstract

High-level Synthesis (HLS) tools have greatly increased the productivity of FPGA application development, making it possible to easily create highly-parallel application-Accelerators. However, while FPGAs are known for the ability to customise the number representation of data-paths, most HLS work only uses custom-precision for fixed-point representations, and for floating-point relies on the 64-, 32-, and 16-bitformats provided by vendors. This paper presents a solution for parametrised floating-point in HLS via C++ templates, allowing for compile-Time selection of exponent and fraction widths, including the use of mixed precisions for input arguments and result types. By using arbitrary width integers and compile-Time logic the resulting operators describe the same data-path as an external floating-point IP generator, while still allowing the HLS tool to perform detailed optimisation and scheduling of the internal components. We show that the resulting custom-width HLS cores provide similar area and performance to platform-native vendor IP blocks, while adding full support for heterogeneous precision floating-point data-paths to HLS tools.

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More information

Published date: 28 April 2019
Additional Information: Funding Information: This research was supported by RAEng/The Leverhulme Trust Senior Research Fellowship grant LTSRF 1718\14\38. Publisher Copyright: © 2019 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.
Venue - Dates: 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019, , San Diego, United States, 2019-04-28 - 2019-05-01
Keywords: custom precision, Floating point, high level synthesis, template hls

Identifiers

Local EPrints ID: 453666
URI: http://eprints.soton.ac.uk/id/eprint/453666
PURE UUID: 4aaecbeb-d035-4448-96c7-a51e8bd65646
ORCID for David B. Thomas: ORCID iD orcid.org/0000-0002-9671-0917

Catalogue record

Date deposited: 20 Jan 2022 17:45
Last modified: 10 Jun 2022 01:57

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Contributors

Author: David B. Thomas ORCID iD

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