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Compile-time generation of custom-precision floating-point IP using HLS tools

Compile-time generation of custom-precision floating-point IP using HLS tools
Compile-time generation of custom-precision floating-point IP using HLS tools

High-Level Synthesis (HLS) tools usually treat floating-point operators as black-box IP cores, and then schedule them as primitives when synthesising code to circuits. This approach relies on a library of IP blocks for chosen floating-point formats, which are pre-characterised to determine latency and area properties needed at compilation time. Two weaknesses of this approach are that it limits the number of floating-point formats - typically to half, single, and double - and that it requires conservative per-cycle scheduling of operators. Modern HLS tools have sophisticated intra-cycle scheduling of integer primitives, as well as C++ front-ends that can execute substantial algorithms at compile-time. This has enabled the creation of platform-independent C++ floating-point libraries which generate custom-precision operators at compile-time, while providing similar or better results as vendor-supplied IP blocks. However, certain problems and questions related to compilation performance and verification remain, so it is not yet clear how widely applicable this technique is.

C++, Compile time IP, Floating point, FPGA, High Level Synthesis, HLS, Meta programming, Templates
192-193
Institute of Electrical and Electronics Engineers Inc.
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Takagi, Naofumi
Boldo, Sylvie
Langhammer, Martin
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Takagi, Naofumi
Boldo, Sylvie
Langhammer, Martin

Thomas, David B. (2019) Compile-time generation of custom-precision floating-point IP using HLS tools. Takagi, Naofumi, Boldo, Sylvie and Langhammer, Martin (eds.) In Proceedings - 26th IEEE Symposium on Computer Arithmetic, ARITH 2019. vol. 2019-June, Institute of Electrical and Electronics Engineers Inc. pp. 192-193 . (doi:10.1109/ARITH.2019.00044).

Record type: Conference or Workshop Item (Paper)

Abstract

High-Level Synthesis (HLS) tools usually treat floating-point operators as black-box IP cores, and then schedule them as primitives when synthesising code to circuits. This approach relies on a library of IP blocks for chosen floating-point formats, which are pre-characterised to determine latency and area properties needed at compilation time. Two weaknesses of this approach are that it limits the number of floating-point formats - typically to half, single, and double - and that it requires conservative per-cycle scheduling of operators. Modern HLS tools have sophisticated intra-cycle scheduling of integer primitives, as well as C++ front-ends that can execute substantial algorithms at compile-time. This has enabled the creation of platform-independent C++ floating-point libraries which generate custom-precision operators at compile-time, while providing similar or better results as vendor-supplied IP blocks. However, certain problems and questions related to compilation performance and verification remain, so it is not yet clear how widely applicable this technique is.

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More information

Published date: 10 June 2019
Additional Information: Publisher Copyright: © 2019 IEEE. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.
Venue - Dates: 26th IEEE Symposium on Computer Arithmetic, ARITH 2019, , Kyoto, Japan, 2019-06-10 - 2019-06-12
Keywords: C++, Compile time IP, Floating point, FPGA, High Level Synthesis, HLS, Meta programming, Templates

Identifiers

Local EPrints ID: 453670
URI: http://eprints.soton.ac.uk/id/eprint/453670
PURE UUID: 05ee442e-7eca-49f3-a8dd-f5b0987e51ba
ORCID for David B. Thomas: ORCID iD orcid.org/0000-0002-9671-0917

Catalogue record

Date deposited: 20 Jan 2022 17:45
Last modified: 10 Jun 2022 01:57

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Contributors

Author: David B. Thomas ORCID iD
Editor: Naofumi Takagi
Editor: Sylvie Boldo
Editor: Martin Langhammer

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