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A high-level design framework for the automatic generation of high-throughput systolic binomial-tree solvers

A high-level design framework for the automatic generation of high-throughput systolic binomial-tree solvers
A high-level design framework for the automatic generation of high-throughput systolic binomial-tree solvers

The binomial-tree model is a numerical method widely used in finance with a computational complexity which is quadratic with respect to the solution accuracy. The existing research has employed reconfigurable computing to provide faster solutions compared with general-purpose processors, but they require low-level manual design by a hardware engineer, and can only solve American options. This paper presents a formal mathematical framework that captures a large class of binomial-tree problems, and provides a systolic data-movement template that maps the framework into digital hardware. This paper also presents a fully automated design flow, which takes C-level user descriptions of binomial trees, with custom data types and tree operations, and automatically generates fully pipelined reconfigurable hardware solutions in field-programmable gate array (FPGA) bit-stream files. On a Xilinx Virtex-7 xc7vx980t FPGA at a 100-MHz clock frequency, we require 54-µs latency to solve three 876-step 32-bit fixed-point American option binomial trees, with a pricing rate of 114k trees/s. From the same device and in comparison to the existing solutions with equivalent FPGA technology, we always achieve better throughput. This ranges from 1.4× throughput compared with a hand-tuned register-transfer level systolic design, to 9.1× and 5.6× improvement with respect to scalar and vector architectures, respectively.

Binomial-tree numerical method, Field-programmable gate arrays (FPGAs), Hardware design automation, High-level synthesis (HLS), Option pricing, Reconfigurable hardware accelerators, Systolic arrays
1063-8210
341-354
Tavakkoli, Aryan
69cf91af-3756-4182-9f36-a6837ad01814
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Tavakkoli, Aryan
69cf91af-3756-4182-9f36-a6837ad01814
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c

Tavakkoli, Aryan and Thomas, David B. (2017) A high-level design framework for the automatic generation of high-throughput systolic binomial-tree solvers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (2), 341-354, [8081850]. (doi:10.1109/TVLSI.2017.2761554).

Record type: Article

Abstract

The binomial-tree model is a numerical method widely used in finance with a computational complexity which is quadratic with respect to the solution accuracy. The existing research has employed reconfigurable computing to provide faster solutions compared with general-purpose processors, but they require low-level manual design by a hardware engineer, and can only solve American options. This paper presents a formal mathematical framework that captures a large class of binomial-tree problems, and provides a systolic data-movement template that maps the framework into digital hardware. This paper also presents a fully automated design flow, which takes C-level user descriptions of binomial trees, with custom data types and tree operations, and automatically generates fully pipelined reconfigurable hardware solutions in field-programmable gate array (FPGA) bit-stream files. On a Xilinx Virtex-7 xc7vx980t FPGA at a 100-MHz clock frequency, we require 54-µs latency to solve three 876-step 32-bit fixed-point American option binomial trees, with a pricing rate of 114k trees/s. From the same device and in comparison to the existing solutions with equivalent FPGA technology, we always achieve better throughput. This ranges from 1.4× throughput compared with a hand-tuned register-transfer level systolic design, to 9.1× and 5.6× improvement with respect to scalar and vector architectures, respectively.

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More information

Published date: 24 October 2017
Additional Information: Publisher Copyright: © 2017 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.
Keywords: Binomial-tree numerical method, Field-programmable gate arrays (FPGAs), Hardware design automation, High-level synthesis (HLS), Option pricing, Reconfigurable hardware accelerators, Systolic arrays

Identifiers

Local EPrints ID: 453672
URI: http://eprints.soton.ac.uk/id/eprint/453672
ISSN: 1063-8210
PURE UUID: cb05af7a-8b9c-4a84-8169-7fb2766a6860
ORCID for David B. Thomas: ORCID iD orcid.org/0000-0002-9671-0917

Catalogue record

Date deposited: 20 Jan 2022 17:45
Last modified: 10 Jun 2022 01:57

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Contributors

Author: Aryan Tavakkoli
Author: David B. Thomas ORCID iD

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