StitchUp: Automatic control flow protection for high level synthesis circuits
StitchUp: Automatic control flow protection for high level synthesis circuits
Soft-error detection in FPGAs typically requires replication, doubling the required area. We propose an approach which distinguishes between tolerable errors in data-flow, such-as arithmetic, and intolerable errors in control-flow, such as branches and their data-dependencies. This approach is demonstrated in a new high-level synthesis compiler pass called StitchUp, which precisely identifies the control critical parts of the design, then automatically replicates only that part. We applied StitchUp to the CHStone benchmark suite and performed exhaustive hardware fault injection in each case, finding that all control-flow errors were detected while only requiring 1% circuit area overhead in the best case.
Fleming, Shane T.
1a7f7be0-0c3f-4125-9298-5b5a6e0bc76e
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
5 June 2016
Fleming, Shane T.
1a7f7be0-0c3f-4125-9298-5b5a6e0bc76e
Thomas, David B.
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Fleming, Shane T. and Thomas, David B.
(2016)
StitchUp: Automatic control flow protection for high level synthesis circuits.
In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016.
vol. 05-09-June-2016,
IEEE..
(doi:10.1145/2897937.2898097).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Soft-error detection in FPGAs typically requires replication, doubling the required area. We propose an approach which distinguishes between tolerable errors in data-flow, such-as arithmetic, and intolerable errors in control-flow, such as branches and their data-dependencies. This approach is demonstrated in a new high-level synthesis compiler pass called StitchUp, which precisely identifies the control critical parts of the design, then automatically replicates only that part. We applied StitchUp to the CHStone benchmark suite and performed exhaustive hardware fault injection in each case, finding that all control-flow errors were detected while only requiring 1% circuit area overhead in the best case.
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Published date: 5 June 2016
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Publisher Copyright:
© 2016 ACM.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
Venue - Dates:
53rd Annual ACM IEEE Design Automation Conference, DAC 2016, , Austin, United States, 2016-06-05 - 2016-06-09
Identifiers
Local EPrints ID: 453688
URI: http://eprints.soton.ac.uk/id/eprint/453688
ISSN: 0738-100X
PURE UUID: 35d18f2f-229d-4c5e-91a9-8470ba16ccb3
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Date deposited: 20 Jan 2022 17:46
Last modified: 17 Mar 2024 04:10
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Author:
Shane T. Fleming
Author:
David B. Thomas
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