Hardware Architectures of Control Algorithms for Cyber-physical Systems Model Identification

Abstract

Applications of multiple model adaptive estimation (MMAE) based controllers are emerging in Cyber-physical systems (CPS). Such control algorithms are computationally intensive as they involve recursive estimation of signals and this thesis investigates the hardware architectures of MMAE algorithm for resource-constrained embedded computing platforms. This thesis presents three original contributions. The first contribution presents a novel hardware architecture for the MMAE based linear time-invariant system model identification. A key feature of the architecture is area efficient which is achieved through the reuse of multipliers and fixed computations in the MMAE filter bank. The proposed architecture is implemented on FPGA and validated for auto-mobile application. It is shown that the proposed architecture has achieved 39% LUT%, 13% FF%, 27% DSP%, and 43% power reduction when compared with directly mapped hardware architecture. The second contribution presents a novel hardware architecture for the linear time-variant (LTV) system model identification, based on the MMAE algorithm. To investigate the area and timing trade-offs, an eight and four multiplier based Kalman filter bank in LTV model identification architecture considered. The architecture has been validated on FPGA for the DC-DC boost converter application with load resistance as an uncertain parameter. From the experimental results, it has been shown that the proposed four multipliers based architecture is area-efficient and 17% LUTs, 14% FFs, 50% DSPs resource and 32% power consumption reduction when compared with an eight multiplier version design with an increase of 50% clock cycles for execution. Furthermore, resource utilization analysis is presented for the higher number (1 to 1024) of filter banks. The final contribution addresses the applicability of the MMAE closed-loop control algorithm for power electronic application, it is shown that the algorithm has significantly improved the closed-loop output voltage response time and settling time when compared with the PID controller and it is demonstrated by the simulation results by changing the load resistance of boost converter abruptly.

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