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Effect of gate dielectric thickness on the performance of top-down ZnO nanowire field-effect transistors

Effect of gate dielectric thickness on the performance of top-down ZnO nanowire field-effect transistors
Effect of gate dielectric thickness on the performance of top-down ZnO nanowire field-effect transistors
The top-down bottom-contact ZnO nanowire field-effect transistors (FETs) utilizing SiO2 as gate dielectric were fabricated and characterize in an attempt to evaluate the device performance effects of gate dielectric thickness variation. In this experiment, four sets of ZnO nanowire FET with gate insulator thicknesses of 0.025 µm, 0.05 µm, 0.075 µm, and 0.10 µm were fabricated. ZnO nanowire were fabricated at room temperature by remote plasma atomic layer deposition (ALD) method. The FETs with 0.10 µm thick gate insulator layer demonstrated better electrical performance as compared to the other devices. The analysis demonstrates that the oxide layer should have the right thickness in order to preserve its insulting capability to function as an insulator layer in fabricated devices.
Springer
Ghazali, Nor Azlin
33bcdbac-4785-419d-be3b-81297f27c0dc
Mohamed, Mohamed Fauzi Packeer
178c9cbe-fa27-4f81-af13-527257be352b
Akbar, Muhammad Firdaus
726d1f59-c3df-4dd9-96b5-e4d5b7c63323
Chong, Harold
795aa67f-29e5-480f-b1bc-9bd5c0d558e1
Ghazali, Nor Azlin
33bcdbac-4785-419d-be3b-81297f27c0dc
Mohamed, Mohamed Fauzi Packeer
178c9cbe-fa27-4f81-af13-527257be352b
Akbar, Muhammad Firdaus
726d1f59-c3df-4dd9-96b5-e4d5b7c63323
Chong, Harold
795aa67f-29e5-480f-b1bc-9bd5c0d558e1

Ghazali, Nor Azlin, Mohamed, Mohamed Fauzi Packeer, Akbar, Muhammad Firdaus and Chong, Harold (2021) Effect of gate dielectric thickness on the performance of top-down ZnO nanowire field-effect transistors. In, Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications. Springer. (In Press) (doi:10.1007/978-981-16-8129-5_105).

Record type: Book Section

Abstract

The top-down bottom-contact ZnO nanowire field-effect transistors (FETs) utilizing SiO2 as gate dielectric were fabricated and characterize in an attempt to evaluate the device performance effects of gate dielectric thickness variation. In this experiment, four sets of ZnO nanowire FET with gate insulator thicknesses of 0.025 µm, 0.05 µm, 0.075 µm, and 0.10 µm were fabricated. ZnO nanowire were fabricated at room temperature by remote plasma atomic layer deposition (ALD) method. The FETs with 0.10 µm thick gate insulator layer demonstrated better electrical performance as compared to the other devices. The analysis demonstrates that the oxide layer should have the right thickness in order to preserve its insulting capability to function as an insulator layer in fabricated devices.

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Paper_EffectofGateofFielectricThickness-Rovisp2021-Rev_4 - Accepted Manuscript
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Accepted/In Press date: 6 September 2021

Identifiers

Local EPrints ID: 456539
URI: http://eprints.soton.ac.uk/id/eprint/456539
PURE UUID: de37e3f1-9f94-4df9-ac64-736a95131ecd
ORCID for Harold Chong: ORCID iD orcid.org/0000-0002-7110-5761

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Date deposited: 04 May 2022 17:14
Last modified: 05 May 2022 01:40

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Contributors

Author: Nor Azlin Ghazali
Author: Mohamed Fauzi Packeer Mohamed
Author: Muhammad Firdaus Akbar
Author: Harold Chong ORCID iD

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