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Pragmatic memory-system support for intermittent computing using emerging non-volatile memory

Pragmatic memory-system support for intermittent computing using emerging non-volatile memory
Pragmatic memory-system support for intermittent computing using emerging non-volatile memory

Intermittent computing (IC) is a key enabler for the vision of a trillion Internet of Things devices. By harvesting energy from the environment, and leveraging non-volatile memory (NVM) to retain computational progress across power cycles, IC enables untethered and battery-free devices to perform computation whenever ambient energy is available. The backbone of state retention is NVM, and recent advances in energy-efficient NVM have the potential to expand the application domain of IC significantly. Utilizing emerging NVM at the level of bitcells, researchers have proposed non-volatile processors. However, these do not leverage hardware-software co-design, which can be used to overcome hardware limitations and to provide support for application-level constraints such as atomicity. In this paper, we propose MEMIC, a memory architecture tailored for IC devices with byte-addressable NVM. A core focus of MEMIC is to combine volatile-and non-volatile memory in such a way that the operations of IC are as efficient as possible, while also maximizing computational performance per joule. MEMIC uses volatile memory for energy efficiency, and nonvolatile memory for data retention. To avoid double-buffered checkpoints and costly roll-backs when code needs to be reexecuted, MEMIC is designed to track and minimize writes to non-volatile memory during failure-atomic sections. Our evaluation shows that MEMIC’s instruction cache reduces workload completion time under intermittent operation by 41-70% and its data cache provides a further reduction of 13-39%.

Codes, Computer bugs, Hardware, Integrated circuits, Nonvolatile memory, Software, Task analysis, embedded systems, hardware-software co-design, intermittent computing, low-power design.
0278-0070
Sliper, Sivert T.
73303db3-fb3d-4434-973b-3def05837e7f
Wang, William
ff81a455-8a66-49db-82f2-849bc6dc2c51
Nikoleris, Nikos
be54f3c1-c36e-4dde-8611-0af54b56e033
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Savanth, Anand
943d0249-4c8e-44c6-9851-713bcd410633
Prabhat, Pranay
6d246b81-a756-431c-865c-2f58e0d03008
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Sliper, Sivert T.
73303db3-fb3d-4434-973b-3def05837e7f
Wang, William
ff81a455-8a66-49db-82f2-849bc6dc2c51
Nikoleris, Nikos
be54f3c1-c36e-4dde-8611-0af54b56e033
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Savanth, Anand
943d0249-4c8e-44c6-9851-713bcd410633
Prabhat, Pranay
6d246b81-a756-431c-865c-2f58e0d03008
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020

Sliper, Sivert T., Wang, William, Nikoleris, Nikos, Weddell, Alexander, Savanth, Anand, Prabhat, Pranay and Merrett, Geoff (2022) Pragmatic memory-system support for intermittent computing using emerging non-volatile memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (doi:10.1109/TCAD.2022.3168263).

Record type: Article

Abstract

Intermittent computing (IC) is a key enabler for the vision of a trillion Internet of Things devices. By harvesting energy from the environment, and leveraging non-volatile memory (NVM) to retain computational progress across power cycles, IC enables untethered and battery-free devices to perform computation whenever ambient energy is available. The backbone of state retention is NVM, and recent advances in energy-efficient NVM have the potential to expand the application domain of IC significantly. Utilizing emerging NVM at the level of bitcells, researchers have proposed non-volatile processors. However, these do not leverage hardware-software co-design, which can be used to overcome hardware limitations and to provide support for application-level constraints such as atomicity. In this paper, we propose MEMIC, a memory architecture tailored for IC devices with byte-addressable NVM. A core focus of MEMIC is to combine volatile-and non-volatile memory in such a way that the operations of IC are as efficient as possible, while also maximizing computational performance per joule. MEMIC uses volatile memory for energy efficiency, and nonvolatile memory for data retention. To avoid double-buffered checkpoints and costly roll-backs when code needs to be reexecuted, MEMIC is designed to track and minimize writes to non-volatile memory during failure-atomic sections. Our evaluation shows that MEMIC’s instruction cache reduces workload completion time under intermittent operation by 41-70% and its data cache provides a further reduction of 13-39%.

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More information

Accepted/In Press date: 12 April 2022
e-pub ahead of print date: 19 April 2022
Published date: 19 April 2022
Keywords: Codes, Computer bugs, Hardware, Integrated circuits, Nonvolatile memory, Software, Task analysis, embedded systems, hardware-software co-design, intermittent computing, low-power design.

Identifiers

Local EPrints ID: 457370
URI: http://eprints.soton.ac.uk/id/eprint/457370
ISSN: 0278-0070
PURE UUID: 944a3137-d33e-4880-bc7d-0be794e63a6d
ORCID for Sivert T. Sliper: ORCID iD orcid.org/0000-0002-8991-3783
ORCID for Alexander Weddell: ORCID iD orcid.org/0000-0002-6763-5460
ORCID for Geoff Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 06 Jun 2022 16:36
Last modified: 24 Jul 2022 01:55

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Contributors

Author: Sivert T. Sliper ORCID iD
Author: William Wang
Author: Nikos Nikoleris
Author: Alexander Weddell ORCID iD
Author: Anand Savanth
Author: Pranay Prabhat
Author: Geoff Merrett ORCID iD

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