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Modelling, initialisation, and time - domain macrosimulation of large digital systems

Modelling, initialisation, and time - domain macrosimulation of large digital systems
Modelling, initialisation, and time - domain macrosimulation of large digital systems

A macrosimulation scheme for the simulation of large digital systems is presented. The scheme involves interactive initialisation, modelling at both the gate and functional levels, and a number of time-domain analysis techniques.Initialisation is performed through the use of 7 logic conditions. The traditional unknown condition X has been split into one indeterminate condition U and two determinate conditions X and R; the advantages of this approach are described. Two extra conditions F and G have also been defined in order to acknowledge the existence of direct analogue transfer functions between input and output voltages. Gates are modelled in the time-domain through explicit equations. The operation of each element is divided in regions where different functions apply. Regions are associated with internal states, and a number pair (state, time in state) contains the information necessary to calculate the next output voltage of each element at a time point. Digital elements are concomitantly simulated irrespective of being gates or functional blocks. Functional models do not provide the same level of detail of gate models: a bottom-up simulation strategy is proposed whereby a collection of gates whose behaviour is well understood is collapsed into a single block; tested parts of the circuit are simulated at this functional level whereas potentially problematic ones are expanded and simulated at the gate level. MASCOT is the set of programs incorporating the ideas and algorithms developed in this work. Its current minicomputer implementation is capable of simulating up to 500 gates or larger circuits involving functional blocks. A number of examples are given to illustrate the use of the program. MASCOT is shown to be two to three orders of magnitude faster than circuit analysers.

University of Southampton
Da Costa, Eduardo Moreira
Da Costa, Eduardo Moreira

Da Costa, Eduardo Moreira (1981) Modelling, initialisation, and time - domain macrosimulation of large digital systems. University of Southampton, Doctoral Thesis.

Record type: Thesis (Doctoral)

Abstract

A macrosimulation scheme for the simulation of large digital systems is presented. The scheme involves interactive initialisation, modelling at both the gate and functional levels, and a number of time-domain analysis techniques.Initialisation is performed through the use of 7 logic conditions. The traditional unknown condition X has been split into one indeterminate condition U and two determinate conditions X and R; the advantages of this approach are described. Two extra conditions F and G have also been defined in order to acknowledge the existence of direct analogue transfer functions between input and output voltages. Gates are modelled in the time-domain through explicit equations. The operation of each element is divided in regions where different functions apply. Regions are associated with internal states, and a number pair (state, time in state) contains the information necessary to calculate the next output voltage of each element at a time point. Digital elements are concomitantly simulated irrespective of being gates or functional blocks. Functional models do not provide the same level of detail of gate models: a bottom-up simulation strategy is proposed whereby a collection of gates whose behaviour is well understood is collapsed into a single block; tested parts of the circuit are simulated at this functional level whereas potentially problematic ones are expanded and simulated at the gate level. MASCOT is the set of programs incorporating the ideas and algorithms developed in this work. Its current minicomputer implementation is capable of simulating up to 500 gates or larger circuits involving functional blocks. A number of examples are given to illustrate the use of the program. MASCOT is shown to be two to three orders of magnitude faster than circuit analysers.

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Published date: 1981

Identifiers

Local EPrints ID: 459004
URI: http://eprints.soton.ac.uk/id/eprint/459004
PURE UUID: 7677999c-024e-4648-8d19-e188514ee062

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Date deposited: 04 Jul 2022 17:02
Last modified: 04 Jul 2022 17:02

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Contributors

Author: Eduardo Moreira Da Costa

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