A study of polysilicon emitter transistors

Wolstenholme, Graham Richard (1988) A study of polysilicon emitter transistors. University of Southampton, Doctoral Thesis.

Abstract

This thesis describes the results of an experimental and theoretical study of the physics of polysilicon emitter transistors. The role of the polysilicon/silicon interface is investigated by comparing the results of electrical measurements and high resolution transmission electron microscopy (HTEM) observations. It is shown that the structure of the interface can be controlled by means of a pre-anneal which is carried out after polysilicon deposition, but before emitter implantation. It is found that the base current and emitter resistance are extremely sensitive to the structure of the interface and can therefore be controlled by a pre-anneal. The HTEM investigations show that a pre-anneal above 900^oC breaks up the interfacial oxide layer which inevitably occurs between the polysilicon and monosilicon regions of the emitter. The extent of the break-up and subsequent epitaxial alignment increases with pre-anneal temperature and complete `balling up' of the interfacial oxide occurs at higher temperatures (1000-1100^oC). This increase in break-up of the interfacial layer correlates with an observed increase in base current of the polysilicon emitter transistor. A simple model is proposed to account for this electrical behaviour. From this model it is shown that for devices with a broken interfacial layer the base current flows primarily through the regions with no interfacial oxide. For these devices the base current is proportional to both the recombination velocity and the fraction of the interface with no interfacial oxide. A novel technique is developed for measuring and separating the interface and polysilicon/metal components of the emitter resistance of a polysilicon emitter transistor. For devices with a continuous interfacial layer, the interface resistance dominates the total emitter resistance and is found to be large (200-450 Ωμm^2) and current dependent. This current dependence is explained in terms of electron tunnelling through the interfacial layer. For devices given a pre-anneal, the interface resistance decreases as the interfacial layer breaks up and a simple model is proposed to explain this behaviour. Predictions from this model indicate that for devices with a balled interfacial layer the interface resistance is low enough (17-33 Ωμm²) for successful scaling of the emitter width to sub-micron geometries. The scalability of polysilicon emitters is investigated by varying the monocrystalline emitter depth from 0.15μm to nominally zero. This is achieved by varying the emitter drive-in time and temperature. Results show that the device characteristics degrade dramatically as the monocrystalline emitter junction depth approaches zero. These devices (termed SIS emitters) are characterized by a non-ideal base current at low forward bias and a low collector current at high forward bias. For devices with a continuous interfacial layer, a kink is observed in the base current at high forward bias. These electrical results are explained in terms of a comprehensive model of an SIS emitter.

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