The development of a high-level synthesis system for concurrent VLSI systems
The development of a high-level synthesis system for concurrent VLSI systems
The development, implementation and testing of a high-level synthesis system, for the automatic generation of concurrent VLSI systems, is described. Special attention was devoted to the following problems: the ability to implement concurrency efficiently; the application to a wide range of digital designs and the synthesis and technology mapping of combinational logic. The input to this system is a high-level functional description of the circuit to be synthesised, which may contain any configuration of sequential and parallel processes. These processes are specified in a single description and do not require to be partitioned or declared separately. This description is globally optimised by means of partitioning, compaction and local transformations, according to a dynamic programming approach. The primary optimisation goal is performance or the generation of a maximally parallel implementation. In the high-level synthesis part, this system is characterised by the use of a `no target architecture' approach, which is implemented by means of a distributed data path and a parallel controller (able to control any number of parallel processes). A technology-independent netlist of parameterised cells and Boolean equations is generated and mapped into a library-based design style. In the logic synthesis part, this system uses multiple level optimisation techniques and technology mapping algorithms to map the combinational logic, present in the design, into library cells. This mapping can be optimised for area or speed. Two distinctive features are the ability to use the more complex cells available in the library and the large degree of independence between the cell library and the synthesis algorithms. The cell library can be easily redefined by the user. These features are achieved by the use of a `string of numbers' representation for the Boolean expressions and the library cells alike, and by performing the mapping directly from the Boolean multiple level representation. The application areas of this system were greatly widened by the ability to optimise a unified parallel description, the generation of a distributed data path and a parallel controller and the use of efficient technology mapping algorithms.
University of Southampton
Bergamaschi, Reinaldo Alvarenga
1988
Bergamaschi, Reinaldo Alvarenga
Bergamaschi, Reinaldo Alvarenga
(1988)
The development of a high-level synthesis system for concurrent VLSI systems.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
The development, implementation and testing of a high-level synthesis system, for the automatic generation of concurrent VLSI systems, is described. Special attention was devoted to the following problems: the ability to implement concurrency efficiently; the application to a wide range of digital designs and the synthesis and technology mapping of combinational logic. The input to this system is a high-level functional description of the circuit to be synthesised, which may contain any configuration of sequential and parallel processes. These processes are specified in a single description and do not require to be partitioned or declared separately. This description is globally optimised by means of partitioning, compaction and local transformations, according to a dynamic programming approach. The primary optimisation goal is performance or the generation of a maximally parallel implementation. In the high-level synthesis part, this system is characterised by the use of a `no target architecture' approach, which is implemented by means of a distributed data path and a parallel controller (able to control any number of parallel processes). A technology-independent netlist of parameterised cells and Boolean equations is generated and mapped into a library-based design style. In the logic synthesis part, this system uses multiple level optimisation techniques and technology mapping algorithms to map the combinational logic, present in the design, into library cells. This mapping can be optimised for area or speed. Two distinctive features are the ability to use the more complex cells available in the library and the large degree of independence between the cell library and the synthesis algorithms. The cell library can be easily redefined by the user. These features are achieved by the use of a `string of numbers' representation for the Boolean expressions and the library cells alike, and by performing the mapping directly from the Boolean multiple level representation. The application areas of this system were greatly widened by the ability to optimise a unified parallel description, the generation of a distributed data path and a parallel controller and the use of efficient technology mapping algorithms.
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Published date: 1988
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Local EPrints ID: 461074
URI: http://eprints.soton.ac.uk/id/eprint/461074
PURE UUID: 8c344ba8-4296-421c-928e-bcd3965ac9e7
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Date deposited: 04 Jul 2022 18:34
Last modified: 04 Jul 2022 18:34
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Author:
Reinaldo Alvarenga Bergamaschi
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