Wafer-scale integration of cellular architectures

Bentley, Leon (1988) Wafer-scale integration of cellular architectures. University of Southampton, Doctoral Thesis.

Abstract

Wafer-scale integration (WSI) is a design technique that enables _ntegrated circuits to be designed as whole-wafer circuits. WSI can offer many advantages compared with conventional chips, and for large systems can result in higher performance, improved reliability, less power consumption and lower assembly costs. However, as the chip area is increased, the production yield decreases because of the presence of small manufacturing defects of the wafer. This thesis describes a fault tolerant design procedure that overcomes the problem caused by wafer defects. Cellular architectures are used because faulty cells can be easily replaced by spares. The proposed scheme uses a variety of repair techniques that are each used at a different level in the system hierarchy. This gives the combined advantages of low-cost repair and good fault isolation. The hierarchical repair procedure was investigated by developing a repair scheme for two-dimensional arrays. Each row is repaired using a self-configuration algorithm known as CRAFT (Configuring Row Algorithm for Fault Tolerance). Programmable links are then used to bypass any rows that fail to configure. This two-level CRAFT repair scheme was computer simulated, and the results were found to compare favourably with two other wafer-scale repair schemes. This thesis also describes an empirical yield model and a novel low-cost programmable link known as bridging-bonds. The bridging-bonds and the results from evaluating two yield analysis chips are then used to design and implement a wafer-scale demonstrator. A full description is given of a 16 x 16 processor array which is implemented on 3 inch (76mm) wafers using the Southampton University 6μm I^2L process. (D82618)

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