A logic synthesis approach to silicon compilation
A logic synthesis approach to silicon compilation
Progress in digital technology has yielded continuing growth in the complexity of circuits that can be packed in a chip. As a consequence, reduced costs and miniaturization widen the range of application of custom-made or VLSI (Very Large Scale Integration) circuits. However, traditional design methodologies have failed to fulfil the requirements of VLSI design. An emerging approach, silicon compilation, proposes VLSI design by automated synthesis of hardware specification from an abstract circuit description. This thesis concerns the development of a low cost VLSI design tool which takes a high level description of a digital circuit and produces a mask layout specification. A circuit description languge, BELA, its compiler, and a functional simulator were designed and implemented. Also, an independent software package was developed to support the compiler in the process of synthesis. The tool is directed towards synchronous circuits; at present, the compiler produces a PLA (Programmable Logic Array) implementation although other implementations are possible. The two main applications envisaged are design of controllers based on finite state machines and design of arithmetic and logic circuit cells. Favourable experimental results concerning those applications were obtained. The distinguishing aspects in this work are the input language and the logic synthesis method developed. A BELA program is an algorithm describing a circuit behaviour; the compiler extracts a physical structure to implement this behaviour. The high level of the input demanded an emphasis on the logic synthesis process. This process integrates various design techniques, including extensive verification and minimization, whose automation benefits from the logic function formalism underlying the synthesis method. (D82642)
University of Southampton
Pádua, Clarindo Isaias Pereira da Silva e
1988
Pádua, Clarindo Isaias Pereira da Silva e
Pádua, Clarindo Isaias Pereira da Silva e
(1988)
A logic synthesis approach to silicon compilation.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
Progress in digital technology has yielded continuing growth in the complexity of circuits that can be packed in a chip. As a consequence, reduced costs and miniaturization widen the range of application of custom-made or VLSI (Very Large Scale Integration) circuits. However, traditional design methodologies have failed to fulfil the requirements of VLSI design. An emerging approach, silicon compilation, proposes VLSI design by automated synthesis of hardware specification from an abstract circuit description. This thesis concerns the development of a low cost VLSI design tool which takes a high level description of a digital circuit and produces a mask layout specification. A circuit description languge, BELA, its compiler, and a functional simulator were designed and implemented. Also, an independent software package was developed to support the compiler in the process of synthesis. The tool is directed towards synchronous circuits; at present, the compiler produces a PLA (Programmable Logic Array) implementation although other implementations are possible. The two main applications envisaged are design of controllers based on finite state machines and design of arithmetic and logic circuit cells. Favourable experimental results concerning those applications were obtained. The distinguishing aspects in this work are the input language and the logic synthesis method developed. A BELA program is an algorithm describing a circuit behaviour; the compiler extracts a physical structure to implement this behaviour. The high level of the input demanded an emphasis on the logic synthesis process. This process integrates various design techniques, including extensive verification and minimization, whose automation benefits from the logic function formalism underlying the synthesis method. (D82642)
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Published date: 1988
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Local EPrints ID: 461928
URI: http://eprints.soton.ac.uk/id/eprint/461928
PURE UUID: 3347fb19-eccd-479a-84a4-bc291cd88ef4
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Date deposited: 04 Jul 2022 18:58
Last modified: 04 Jul 2022 18:58
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Author:
Clarindo Isaias Pereira da Silva e Pádua
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