Studies of polysilicon emitter transistors and their applications to high speed logic circuits
Studies of polysilicon emitter transistors and their applications to high speed logic circuits
Studies have been carried out to investigate how polysilicon emitter transistors can be used to improve the speed of ECL circuits. It has been found that the much enhanced current gain of such transistors with an interfacial layer allows a five-fold increase in the base doping, and consequently leads to an approximate 30% improvement in the circuit speed (from 2.37 to 1.70ns) at 6μm geometries. This is achieved at the expense of a lower gain by six to seven times, a higher base-emitter junction capacitance and a lower unity gain bandwidth f_T. An optimum circuit speed of 320ps is predicted at 6μm geometries. A modified self-aligned process, which uses phosphorus instead of arsenic as the emitter dopant and regrown amorphous rather than as-deposited polysilicon to contact to the emitter, has been developed. This has led to a three times reduction in the emitter resistance of the self-aligned transistors, and produced devices with a fT of 7.30GHz. The self-alignment technique has also further improved the circuit speed by a factor of approximately three, to a value of 630ps at 6μm geometries. An optimum circuit speed of 160ps is predicted at this geometry. Emitter resistance has been identified as a potential problem for polysilicon emitter transistors. An excessive emitter resistance is undesirable because it decreases the voltage swing and noise margins of logic circuits, and eventually can upset the proper switching of the circuit. It has been shown that the presence of an interfacial layer in the polysilicon emitter transistor leads to a significantly higher emitter resistance. In addition, phosphorus-doped transistors are found to have a considerably lower emitter resistance than arsenic-doped ones. These results can be fully explained using tunnelling theory. An analytical expression for the gate-delay of an ECL gate has been derived numerically, and its accuracy demonstrated experimentally. Using this expression, a scaling study has been carried out. It is predicted that the trade-off between base doping and gain does not give improved speed at sub-micron geometries. This is because f_T is the most important speed limiting factor at these geometries. It is shown that the optimum process at sub-micron geometries is a self-aligned one without an interfacial layer, and using a low base doping and a narrowbase width in order to achieve a very high f_T. A propagation delay of approximately 50ps is predicted for our process at a linewidth of 0.35μm. (D72187/87)
University of Southampton
1986
Chor, Eng-Fong
(1986)
Studies of polysilicon emitter transistors and their applications to high speed logic circuits.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
Studies have been carried out to investigate how polysilicon emitter transistors can be used to improve the speed of ECL circuits. It has been found that the much enhanced current gain of such transistors with an interfacial layer allows a five-fold increase in the base doping, and consequently leads to an approximate 30% improvement in the circuit speed (from 2.37 to 1.70ns) at 6μm geometries. This is achieved at the expense of a lower gain by six to seven times, a higher base-emitter junction capacitance and a lower unity gain bandwidth f_T. An optimum circuit speed of 320ps is predicted at 6μm geometries. A modified self-aligned process, which uses phosphorus instead of arsenic as the emitter dopant and regrown amorphous rather than as-deposited polysilicon to contact to the emitter, has been developed. This has led to a three times reduction in the emitter resistance of the self-aligned transistors, and produced devices with a fT of 7.30GHz. The self-alignment technique has also further improved the circuit speed by a factor of approximately three, to a value of 630ps at 6μm geometries. An optimum circuit speed of 160ps is predicted at this geometry. Emitter resistance has been identified as a potential problem for polysilicon emitter transistors. An excessive emitter resistance is undesirable because it decreases the voltage swing and noise margins of logic circuits, and eventually can upset the proper switching of the circuit. It has been shown that the presence of an interfacial layer in the polysilicon emitter transistor leads to a significantly higher emitter resistance. In addition, phosphorus-doped transistors are found to have a considerably lower emitter resistance than arsenic-doped ones. These results can be fully explained using tunnelling theory. An analytical expression for the gate-delay of an ECL gate has been derived numerically, and its accuracy demonstrated experimentally. Using this expression, a scaling study has been carried out. It is predicted that the trade-off between base doping and gain does not give improved speed at sub-micron geometries. This is because f_T is the most important speed limiting factor at these geometries. It is shown that the optimum process at sub-micron geometries is a self-aligned one without an interfacial layer, and using a low base doping and a narrowbase width in order to achieve a very high f_T. A propagation delay of approximately 50ps is predicted for our process at a linewidth of 0.35μm. (D72187/87)
This record has no associated files available for download.
More information
Published date: 1986
Identifiers
Local EPrints ID: 461977
URI: http://eprints.soton.ac.uk/id/eprint/461977
PURE UUID: c3e57d09-5074-4c4d-b755-a3026174cb6e
Catalogue record
Date deposited: 04 Jul 2022 18:59
Last modified: 04 Jul 2022 18:59
Export record
Contributors
Author:
Eng-Fong Chor
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics