Modelling of small geometry SOI MOSFET's for use in simulators
Modelling of small geometry SOI MOSFET's for use in simulators
A general surface-potential based model for a small geometry SOI MOSFET and a long channel model for an ultra-thin SOI MOSFET have been developed and implemented into SPICE 3E2.
In the thesis, the surface potentials of the double-gate controlled device are studied in detail by using the determine and solve algorithms developed. The dominant surface, strong and weak coupling, and the channel shielding effect, between the two surfaces, are also researched. Based on these surface conditions, new operation modes of an SOI MOSFET are then classified to allow a general modelling of the device.
The effective channel charge concentration, which is calculated from the real surface potential, rather than a fixed surface potential, defined from the general current density equation considering both drift and diffusion current components, is used both for the drain current formulation for DC analysis and for the terminal charges formulation for transient and small signal analysis. The second order effects are also included in the formulation for transient and AC analysis. The models developed can thus be used for every operation mode and are valid for surface condition through weak to strong inversion.
The small geometry effects and second effects are also studied; the same features are investigated for the modelling of channel length modulation, charge sharing, impact ionisation and bipolar snap-back effects. The effective channel charge concentration at the source end is used also for the modelling of the mobility degradation. The model, therefore, needs no onset inversion potential and threshold expressions in the evaluation subroutine of the simulator.
The novel simplified equivalent circuits for DC, transient, and AC analysis, and their companion networks are also developed. The bi-direction behaviour of the device and the interchangeability between the front gate and back gate are taken into account.
University of Southampton
1993
Lin, Jyi Tsong
(1993)
Modelling of small geometry SOI MOSFET's for use in simulators.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
A general surface-potential based model for a small geometry SOI MOSFET and a long channel model for an ultra-thin SOI MOSFET have been developed and implemented into SPICE 3E2.
In the thesis, the surface potentials of the double-gate controlled device are studied in detail by using the determine and solve algorithms developed. The dominant surface, strong and weak coupling, and the channel shielding effect, between the two surfaces, are also researched. Based on these surface conditions, new operation modes of an SOI MOSFET are then classified to allow a general modelling of the device.
The effective channel charge concentration, which is calculated from the real surface potential, rather than a fixed surface potential, defined from the general current density equation considering both drift and diffusion current components, is used both for the drain current formulation for DC analysis and for the terminal charges formulation for transient and small signal analysis. The second order effects are also included in the formulation for transient and AC analysis. The models developed can thus be used for every operation mode and are valid for surface condition through weak to strong inversion.
The small geometry effects and second effects are also studied; the same features are investigated for the modelling of channel length modulation, charge sharing, impact ionisation and bipolar snap-back effects. The effective channel charge concentration at the source end is used also for the modelling of the mobility degradation. The model, therefore, needs no onset inversion potential and threshold expressions in the evaluation subroutine of the simulator.
The novel simplified equivalent circuits for DC, transient, and AC analysis, and their companion networks are also developed. The bi-direction behaviour of the device and the interchangeability between the front gate and back gate are taken into account.
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Published date: 1993
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Local EPrints ID: 462196
URI: http://eprints.soton.ac.uk/id/eprint/462196
PURE UUID: 70746a43-0698-430c-9b5b-9e43975d6f0d
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Date deposited: 04 Jul 2022 19:03
Last modified: 04 Jul 2022 19:03
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Author:
Jyi Tsong Lin
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