Reliable communication protocols for high-performance computing
Reliable communication protocols for high-performance computing
Modern multicomputer architectures provide high-performance hardware support for the error-free delivery of interprocessor messages. This thesis describes the design of reliable lightweight communication protocols which allow these architectures to be programmed efficiently using message-passing interfaces. A major objective of this work is to produce deadlock-free communication systems that can operate with bounded memory requirements. This allows message delivery to be guaranteed in the absence of hardware faults. Rigorous techniques are employed to ensure that these complex communication systems can be implemented correctly.
A Universal Packet Routing Interface has been developed which exploits modern multicomputer architectures effectively, while maintaining a good match to parallel programming environments. The interface permits message-passing protocols to be synthesized by considering the activities at the protocol end-points alone. Two implementations of the interface for first-generation transputers are considered. The first system employs a software router to provide deadlock-free routing on arbitrary topologies. The second implementation delegates the routing cost onto a hardware communication subsystem to yield up to a five-fold increase in attainable bandwidth.
Analytical and formal methods are used to synthesize a virtual channel protocol upon the packet-level primitives of the UPRI. Exhaustive verification of the implementation is employed to check its correctness. The interface to this protocol is compatible with the communication facilities of future machines based on Inmos T9000 processors and C104 routers. This allows the architecture of second-generation Inmos components to be emulated using first-generation machines.
An alternative organization for a message-passing interface is to allow messages to be directly addressed to their destination. An elegant interface of this type is developed in a manner that enables implementations with bounded memory requirements. This arrangement forces programmers to consider the inherent buffering requirements of their communication patterns and this enhances application portability. (DX178949)
University of Southampton
1993
Debbage, Mark
(1993)
Reliable communication protocols for high-performance computing.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
Modern multicomputer architectures provide high-performance hardware support for the error-free delivery of interprocessor messages. This thesis describes the design of reliable lightweight communication protocols which allow these architectures to be programmed efficiently using message-passing interfaces. A major objective of this work is to produce deadlock-free communication systems that can operate with bounded memory requirements. This allows message delivery to be guaranteed in the absence of hardware faults. Rigorous techniques are employed to ensure that these complex communication systems can be implemented correctly.
A Universal Packet Routing Interface has been developed which exploits modern multicomputer architectures effectively, while maintaining a good match to parallel programming environments. The interface permits message-passing protocols to be synthesized by considering the activities at the protocol end-points alone. Two implementations of the interface for first-generation transputers are considered. The first system employs a software router to provide deadlock-free routing on arbitrary topologies. The second implementation delegates the routing cost onto a hardware communication subsystem to yield up to a five-fold increase in attainable bandwidth.
Analytical and formal methods are used to synthesize a virtual channel protocol upon the packet-level primitives of the UPRI. Exhaustive verification of the implementation is employed to check its correctness. The interface to this protocol is compatible with the communication facilities of future machines based on Inmos T9000 processors and C104 routers. This allows the architecture of second-generation Inmos components to be emulated using first-generation machines.
An alternative organization for a message-passing interface is to allow messages to be directly addressed to their destination. An elegant interface of this type is developed in a manner that enables implementations with bounded memory requirements. This arrangement forces programmers to consider the inherent buffering requirements of their communication patterns and this enhances application portability. (DX178949)
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Published date: 1993
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Local EPrints ID: 462398
URI: http://eprints.soton.ac.uk/id/eprint/462398
PURE UUID: a4689571-9a1f-4407-9a3c-bb5af4255955
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Date deposited: 04 Jul 2022 19:07
Last modified: 04 Jul 2022 19:07
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Author:
Mark Debbage
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