The design and implementation of an analogue circuit simulator on transputers
The design and implementation of an analogue circuit simulator on transputers
This thesis describes the implementation of a new analogue circuit simulation program on transputers (ASCOT). The primary objective of the system is to improve the performance of electronic circuit simulation without compromising accuracy. Circuit simulation is an extremely time consuming and numerically intensive application, and the time complexity is such that it is not really feasible (at present) to simulate circuits at the device level with more than, maybe, 1000 nodes [Brow92]. This figure is trailing considerably behind the fabrication abilities of today's technology.
Much effort, therefore, is currently focused on ways of improving the speed of circuit simulation, and one promising idea is to use parallel processing. An analysis of the distribution of CPU time in a circuit simulator shows that two steps in particular form a computational bottleneck: the matrix building process and the matrix solution process. Whilst it is not possible to parallel the processes themselves, it is feasible to parallelise their internal workings. This thesis attacks both these problem areas.
At the heart of the solution process is the requirement to invert a large set of linear simultaneous equations. A new method of recursive partitioning for such systems, based on Jacobi's method and implemented on a balanced binary tree of T800 transputers, is described. A host transputer provides the interface to the user and peripherals, and is responsible for scheduling data transfers and checking for convergence. The solution process is carried out by the transputer tree. Results are presented for the system, implemented in OCCAM, and compared with the same algorithm, written in C and run on a (sequential) micro VAX II.
Two novel parallel approaches to handle the Newton-Raphson loop and, in particular, the matrix building process (device evaluation and stamp derivation) are also presented. The first technique, based on the idea of partitioning the device set, introduces large communication overheads. The second technique, where the partitioning is node-, rather than device based, shows no such bottlenecks. In both implementations, the multi-process solver itself is responsible for managing dynamic memory allocation.
University of Southampton
1994
Bouchlaghem, Yassine
(1994)
The design and implementation of an analogue circuit simulator on transputers.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
This thesis describes the implementation of a new analogue circuit simulation program on transputers (ASCOT). The primary objective of the system is to improve the performance of electronic circuit simulation without compromising accuracy. Circuit simulation is an extremely time consuming and numerically intensive application, and the time complexity is such that it is not really feasible (at present) to simulate circuits at the device level with more than, maybe, 1000 nodes [Brow92]. This figure is trailing considerably behind the fabrication abilities of today's technology.
Much effort, therefore, is currently focused on ways of improving the speed of circuit simulation, and one promising idea is to use parallel processing. An analysis of the distribution of CPU time in a circuit simulator shows that two steps in particular form a computational bottleneck: the matrix building process and the matrix solution process. Whilst it is not possible to parallel the processes themselves, it is feasible to parallelise their internal workings. This thesis attacks both these problem areas.
At the heart of the solution process is the requirement to invert a large set of linear simultaneous equations. A new method of recursive partitioning for such systems, based on Jacobi's method and implemented on a balanced binary tree of T800 transputers, is described. A host transputer provides the interface to the user and peripherals, and is responsible for scheduling data transfers and checking for convergence. The solution process is carried out by the transputer tree. Results are presented for the system, implemented in OCCAM, and compared with the same algorithm, written in C and run on a (sequential) micro VAX II.
Two novel parallel approaches to handle the Newton-Raphson loop and, in particular, the matrix building process (device evaluation and stamp derivation) are also presented. The first technique, based on the idea of partitioning the device set, introduces large communication overheads. The second technique, where the partitioning is node-, rather than device based, shows no such bottlenecks. In both implementations, the multi-process solver itself is responsible for managing dynamic memory allocation.
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Published date: 1994
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Local EPrints ID: 462505
URI: http://eprints.soton.ac.uk/id/eprint/462505
PURE UUID: 6e7ba8eb-a49e-4ba7-b1cf-79b41c6d1936
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Date deposited: 04 Jul 2022 19:10
Last modified: 04 Jul 2022 19:10
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Author:
Yassine Bouchlaghem
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