Design and implementation of a RISC processor for computer image generation geometric patterns
Design and implementation of a RISC processor for computer image generation geometric patterns
This thesis describes the analysis, prototype implementation, and VLSI design of a RISC processor which is capable of performing the geometric computations in computer generated imagery (CGI) systems at very high speeds. The analysis of high-performance CGI systems and graphics processors, indicates that the processing power required to accomplish geometric computations at high speed demands the use of multiple processors operating concurrently. These processors must have hardware support for fast arithmetic operations, particularly multiplication and division. The examination of geometric procedures and program measurements on a real-time CGI application, leads to the definition of a suitable instruction set and provides important findings to accomplish geometric operations in high speed. Based on these findings, a parallel processing architecture using several RISC processors operating concurrently is discussed and the architecture of a dedicated RISC for geometric computations is developed. Emphasis is given to the ability to transfer data into and out of the processor at high speed, the implementation of fast multiplication and division operations, the development of a parameter passing mechanism for table driven parameters, and an optimised implementation of pipeline stages. A novel method to transfer data into and out of the processor extremely fast is developed, together with the design of a three-port/three-access memory cell for a register file. Several signed methods of division are examined and significant improvements over existing implementations are achieved through a novel implementation of a radix-4 method, together with an improvement of a radix-2 method. A hardware prototype has been developed and is described. Simulations of the VLSI standard cell implementation indicate that this processor can run at 30MHz (30 MIPS peak), which corresponds to a capability of processing the geometric computations of as least 30,000 polygons per second. Using four identical processors operating in parallel, it is possible to obtain a geometric computation system that can process more than 100,000 polygons per second.
University of Southampton
1990
Anido, Manuel Lois
(1990)
Design and implementation of a RISC processor for computer image generation geometric patterns.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
This thesis describes the analysis, prototype implementation, and VLSI design of a RISC processor which is capable of performing the geometric computations in computer generated imagery (CGI) systems at very high speeds. The analysis of high-performance CGI systems and graphics processors, indicates that the processing power required to accomplish geometric computations at high speed demands the use of multiple processors operating concurrently. These processors must have hardware support for fast arithmetic operations, particularly multiplication and division. The examination of geometric procedures and program measurements on a real-time CGI application, leads to the definition of a suitable instruction set and provides important findings to accomplish geometric operations in high speed. Based on these findings, a parallel processing architecture using several RISC processors operating concurrently is discussed and the architecture of a dedicated RISC for geometric computations is developed. Emphasis is given to the ability to transfer data into and out of the processor at high speed, the implementation of fast multiplication and division operations, the development of a parameter passing mechanism for table driven parameters, and an optimised implementation of pipeline stages. A novel method to transfer data into and out of the processor extremely fast is developed, together with the design of a three-port/three-access memory cell for a register file. Several signed methods of division are examined and significant improvements over existing implementations are achieved through a novel implementation of a radix-4 method, together with an improvement of a radix-2 method. A hardware prototype has been developed and is described. Simulations of the VLSI standard cell implementation indicate that this processor can run at 30MHz (30 MIPS peak), which corresponds to a capability of processing the geometric computations of as least 30,000 polygons per second. Using four identical processors operating in parallel, it is possible to obtain a geometric computation system that can process more than 100,000 polygons per second.
This record has no associated files available for download.
More information
Published date: 1990
Identifiers
Local EPrints ID: 462535
URI: http://eprints.soton.ac.uk/id/eprint/462535
PURE UUID: 4747b072-a299-49e0-aa1d-caa14b414213
Catalogue record
Date deposited: 04 Jul 2022 19:16
Last modified: 04 Jul 2022 19:16
Export record
Contributors
Author:
Manuel Lois Anido
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics