The practical implications of the boundary-scan standard
The practical implications of the boundary-scan standard
This thesis is concerned with the practical implications of manufacture testing of loaded printed circuit boards that are either fully or partially populated with chips that are equipped with IEEE 1149.1 Boundary-Scan.
The work contained in this thesis is in 4 main areas; interconnect testing using boundary-scan, operating the boundary-scan architecture, verifying the manufacture of the boundary-scan architecture, and coping with partial implementations of boundary-scan.
One of the main features of boundary-scan is the partitioning between the function of chips and their interconnect on the board. The algorithms that have been proposed for generating test sets for testing interconnect are analysed closely, and their performance for realistically-sized boards is assessed. An algorithm is also proposed for testing bus-structured systems; this produces test sequences shorter than previously suggested, and caters for common bus enables and CMOS charge-storing problems.
The requirements of the software that is necessary to access boundary-scan are analysed, leading to a specification of the tasks in the test compilation process. This software has been implemented, with particular attention paid to the boundary-scan design variations that the standard permits.
Before the boundary-scan architecture can be used to test other parts of a board, it must be verified that this has been manufactured correctly. The standard provides a means to do this, and the detection and diagnosis capabilities of this are analysed using a real circuit. This has led to modifications in the test procedure to improve its effectiveness.
A particular problem is whether boards are designed where some of the chips on the board do not have boundary-scan; this situation is analysed, and possible solutions are suggested. A classification of the type of interconnect nets that can be encountered on a board is made, and this is then used to assess the detection and diagnostic performance of these solutions.
University of Southampton
1994
Dickinson, Paul John
(1994)
The practical implications of the boundary-scan standard.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
This thesis is concerned with the practical implications of manufacture testing of loaded printed circuit boards that are either fully or partially populated with chips that are equipped with IEEE 1149.1 Boundary-Scan.
The work contained in this thesis is in 4 main areas; interconnect testing using boundary-scan, operating the boundary-scan architecture, verifying the manufacture of the boundary-scan architecture, and coping with partial implementations of boundary-scan.
One of the main features of boundary-scan is the partitioning between the function of chips and their interconnect on the board. The algorithms that have been proposed for generating test sets for testing interconnect are analysed closely, and their performance for realistically-sized boards is assessed. An algorithm is also proposed for testing bus-structured systems; this produces test sequences shorter than previously suggested, and caters for common bus enables and CMOS charge-storing problems.
The requirements of the software that is necessary to access boundary-scan are analysed, leading to a specification of the tasks in the test compilation process. This software has been implemented, with particular attention paid to the boundary-scan design variations that the standard permits.
Before the boundary-scan architecture can be used to test other parts of a board, it must be verified that this has been manufactured correctly. The standard provides a means to do this, and the detection and diagnosis capabilities of this are analysed using a real circuit. This has led to modifications in the test procedure to improve its effectiveness.
A particular problem is whether boards are designed where some of the chips on the board do not have boundary-scan; this situation is analysed, and possible solutions are suggested. A classification of the type of interconnect nets that can be encountered on a board is made, and this is then used to assess the detection and diagnostic performance of these solutions.
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Published date: 1994
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Local EPrints ID: 462837
URI: http://eprints.soton.ac.uk/id/eprint/462837
PURE UUID: 43f372ea-ea53-4655-8ba1-7c3d2b24a857
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Date deposited: 04 Jul 2022 20:13
Last modified: 04 Jul 2022 20:13
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Author:
Paul John Dickinson
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