Current domain analogue-to-digital conversion techniques for CMOS VLSI
Current domain analogue-to-digital conversion techniques for CMOS VLSI
A new circuit technique has been proposed, Switched-Current (SI), which facilitates the construction of transistor-only current-mode analogue sampled-data circuits, and is hence more compatible with emerging processes. This thesis addresses the design of SI A/D converters with emphasis on video frequency requirements.
The subject is introduced with a review of SI technology and basic cell performance. Where possible, comparison is made with SC alternatives. Design considerations are then set out for wide bandwidth, high sample rate SI/AD converter subcells including double sampling memory elements, current-mode regenerative comparators, current-source D/A converters, Euler integrators, and V/I converters. Architectural studies for the realisation of Nyquist SI A/D converters are presented, and bandwidth limitations and linearity concerns identified. It is suggested that such converters are best implemented using pipelined techniques with a modest number of bits per stage. The design of a 15MS/s, 8-bit differential pipelined A/D converter is described in some detail. Novel features of this design include the use of buffer memory cells to ensure accurate analogue signal propagation throughout the pipeline, and a new regenerative SI current comparator with offset compensation. Experimental results from two versions of the A/D (15MS/s and 60MS/s) fabricated in a 0.8um CMOS process are described and full Nyquist performance is demonstrated.
The realisation of SI oversampled (ΣΔ) A/D converters is also considered in this thesis. A low frequency (4MS/s, 8kHz bandwidth, 9-bit dynamic range) design example fabricated in 0.8um CMOS is described, and experimental results presented which agree well with simulations from a high level model. High frequency applications (100MS/s, 6MHz bandwidth, 10-bit dynamic range) are also investigated and the merits of multi-loop versus single-loop structures are analysed.
University of Southampton
Bracey, Mark
3058275c-d850-4ac5-984e-353414c59d45
1997
Bracey, Mark
3058275c-d850-4ac5-984e-353414c59d45
Bracey, Mark
(1997)
Current domain analogue-to-digital conversion techniques for CMOS VLSI.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
A new circuit technique has been proposed, Switched-Current (SI), which facilitates the construction of transistor-only current-mode analogue sampled-data circuits, and is hence more compatible with emerging processes. This thesis addresses the design of SI A/D converters with emphasis on video frequency requirements.
The subject is introduced with a review of SI technology and basic cell performance. Where possible, comparison is made with SC alternatives. Design considerations are then set out for wide bandwidth, high sample rate SI/AD converter subcells including double sampling memory elements, current-mode regenerative comparators, current-source D/A converters, Euler integrators, and V/I converters. Architectural studies for the realisation of Nyquist SI A/D converters are presented, and bandwidth limitations and linearity concerns identified. It is suggested that such converters are best implemented using pipelined techniques with a modest number of bits per stage. The design of a 15MS/s, 8-bit differential pipelined A/D converter is described in some detail. Novel features of this design include the use of buffer memory cells to ensure accurate analogue signal propagation throughout the pipeline, and a new regenerative SI current comparator with offset compensation. Experimental results from two versions of the A/D (15MS/s and 60MS/s) fabricated in a 0.8um CMOS process are described and full Nyquist performance is demonstrated.
The realisation of SI oversampled (ΣΔ) A/D converters is also considered in this thesis. A low frequency (4MS/s, 8kHz bandwidth, 9-bit dynamic range) design example fabricated in 0.8um CMOS is described, and experimental results presented which agree well with simulations from a high level model. High frequency applications (100MS/s, 6MHz bandwidth, 10-bit dynamic range) are also investigated and the merits of multi-loop versus single-loop structures are analysed.
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Published date: 1997
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Local EPrints ID: 463025
URI: http://eprints.soton.ac.uk/id/eprint/463025
PURE UUID: 3b00d478-5e30-4ed9-b5bc-7358c7470855
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Date deposited: 04 Jul 2022 20:39
Last modified: 04 Jul 2022 20:39
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Author:
Mark Bracey
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