Compact modelling of partially depleted silicon-on-insulator MOSFETS for analogue circuit simulation
Compact modelling of partially depleted silicon-on-insulator MOSFETS for analogue circuit simulation
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater problems as device geometries shrink. Thus the search for a suitable replacement has begun and Silicon-On-Insulator (SOI) technology has been proposed as a promising candidate. Due to manufacturing issues, the partially depleted (PD) variant of the SOI MOSFET is receiving much of the interest. Unfortunately, because of their structure, SOUI MOSFETs exhibit many anomalous static and dynamic effects which can be attributed to either the floating body or to self-heating. For confident design of analogue circuits and high-performance digital cells, a compact model of the PD SOI MOSFET, which includes these effects, must be available to the designer. This work aims to produce such a model and to implement it into a circuit simulator.
The development of the Southampton Thermal AnaloGue (or STAG) model is presented in this thesis. The model is physically based, charge conserving and formulated in terms of the device surface potential. A novel approach in model formulation ensures model continuity and robustness which together with new, more stringent numerical measures, aid convergence in circuit simulations. The model accounts for both floating body and self-heating effects in the static and dynamic domains, as well as standard second order effects and parasitics.
The STAG model has been implemented into the SPICE3f5 circuit simulator, and results from a wide ranging model evaluation exercise are presented. Qualitative tests show that the model is well behaved and accounts for both the floating body and self-heating effects. Comparisons with measured device data show a good agreement, not only in the current characteristics, but also in conductance domain. The model's robustness in the context of circuit simulation is also tested and found to be excellent. Furthermore, simulation results from fabricated circuits also compare well with measured circuit performance. Finally, it is shown that the STAG model can be used to provide further insight into the impact of both floating body and self-heating effects on dynamic circuit operation. These results indicate that the STAG model is a useable and robust tool for the designer of analogue circuits using PD SOI MOS technology.
University of Southampton
1997
Lee, Michael Siu Lun
(1997)
Compact modelling of partially depleted silicon-on-insulator MOSFETS for analogue circuit simulation.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater problems as device geometries shrink. Thus the search for a suitable replacement has begun and Silicon-On-Insulator (SOI) technology has been proposed as a promising candidate. Due to manufacturing issues, the partially depleted (PD) variant of the SOI MOSFET is receiving much of the interest. Unfortunately, because of their structure, SOUI MOSFETs exhibit many anomalous static and dynamic effects which can be attributed to either the floating body or to self-heating. For confident design of analogue circuits and high-performance digital cells, a compact model of the PD SOI MOSFET, which includes these effects, must be available to the designer. This work aims to produce such a model and to implement it into a circuit simulator.
The development of the Southampton Thermal AnaloGue (or STAG) model is presented in this thesis. The model is physically based, charge conserving and formulated in terms of the device surface potential. A novel approach in model formulation ensures model continuity and robustness which together with new, more stringent numerical measures, aid convergence in circuit simulations. The model accounts for both floating body and self-heating effects in the static and dynamic domains, as well as standard second order effects and parasitics.
The STAG model has been implemented into the SPICE3f5 circuit simulator, and results from a wide ranging model evaluation exercise are presented. Qualitative tests show that the model is well behaved and accounts for both the floating body and self-heating effects. Comparisons with measured device data show a good agreement, not only in the current characteristics, but also in conductance domain. The model's robustness in the context of circuit simulation is also tested and found to be excellent. Furthermore, simulation results from fabricated circuits also compare well with measured circuit performance. Finally, it is shown that the STAG model can be used to provide further insight into the impact of both floating body and self-heating effects on dynamic circuit operation. These results indicate that the STAG model is a useable and robust tool for the designer of analogue circuits using PD SOI MOS technology.
This record has no associated files available for download.
More information
Published date: 1997
Identifiers
Local EPrints ID: 463282
URI: http://eprints.soton.ac.uk/id/eprint/463282
PURE UUID: 2a87d256-d0a4-449f-89a6-dfbb0b36bed4
Catalogue record
Date deposited: 04 Jul 2022 20:48
Last modified: 04 Jul 2022 20:48
Export record
Contributors
Author:
Michael Siu Lun Lee
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics