Novel IC test methodologies : evaluation of AC RMS supply current monitoring
Novel IC test methodologies : evaluation of AC RMS supply current monitoring
Measurement of the RMS value of the AC component of the supply current drawn by an Integrated Circuit (IC) when stimulated with a sinusoid (the IRMS test) is proposed as a fast simple and inexpensive alternative to full performance testing for faults caused during manufacture in analogue and mixed-signal ICs. This thesis presents an evaluation of this technique comparing it to Transient Response Testing (TRT) and Dynamic Supply Current Monitoring (DSCM). Monte Carlo statistical fault simulation with HSPICE is proposed to derive a threshold of detection between a faulty and a fault free circuit, assuming the RMS current measured from ICs of the same batch will vary due to process parameter spread. A major problem in carrying out this comparative study was the excessive simulation time, but by modelling circuits behaviourally using a new macromodel that included AC supply current modelling, and only simulating a representative sample of fault responses from the circuit, the time to simulate all likely catastrophic faults (opens and short circuits) was reduced by over 10 times.
The number of faults detected with the IRMS test was dependent on the frequency, amplitude and DC offset of the sinusoidal stimulus. An Automatic Test Stimulus Generation (ATSG) algorithm was proposed and demonstrated. This algorithm selected the frequency and DC offset of the stimulus that caused the circuit response to have a high sensitivity to fault but a low sensitivity to process parameter deviation using a newly defined metric: Process Weighted Sensitivity (PWS). The amplitude of the sinusoid stimulus is minimised to ensure linearity of response but not so that the response is lost in noise. The total number of Monte Carlo transient fault simulations is reduced by searching the input space using fast AC small signal analysis for stimuli most likely to detect the fault. Using this algorithm an increase in fault coverage for a multiplier circuit from 30% to over 70% was achieved. The generality of ATSG algorithm was extended to include the generation of stimuli for static DC supply current tests using a technique analogous to the sensitive path algorithm used for automatic test pattern generation for digital circuits. The fast DC test is applied first to remove those faults that cause gross malfunction of the circuit followed by more sophisticated and expensive time domain IRMS test to detect those faults remaining.
University of Southampton
1998
Chalk, Christopher David
(1998)
Novel IC test methodologies : evaluation of AC RMS supply current monitoring.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
Measurement of the RMS value of the AC component of the supply current drawn by an Integrated Circuit (IC) when stimulated with a sinusoid (the IRMS test) is proposed as a fast simple and inexpensive alternative to full performance testing for faults caused during manufacture in analogue and mixed-signal ICs. This thesis presents an evaluation of this technique comparing it to Transient Response Testing (TRT) and Dynamic Supply Current Monitoring (DSCM). Monte Carlo statistical fault simulation with HSPICE is proposed to derive a threshold of detection between a faulty and a fault free circuit, assuming the RMS current measured from ICs of the same batch will vary due to process parameter spread. A major problem in carrying out this comparative study was the excessive simulation time, but by modelling circuits behaviourally using a new macromodel that included AC supply current modelling, and only simulating a representative sample of fault responses from the circuit, the time to simulate all likely catastrophic faults (opens and short circuits) was reduced by over 10 times.
The number of faults detected with the IRMS test was dependent on the frequency, amplitude and DC offset of the sinusoidal stimulus. An Automatic Test Stimulus Generation (ATSG) algorithm was proposed and demonstrated. This algorithm selected the frequency and DC offset of the stimulus that caused the circuit response to have a high sensitivity to fault but a low sensitivity to process parameter deviation using a newly defined metric: Process Weighted Sensitivity (PWS). The amplitude of the sinusoid stimulus is minimised to ensure linearity of response but not so that the response is lost in noise. The total number of Monte Carlo transient fault simulations is reduced by searching the input space using fast AC small signal analysis for stimuli most likely to detect the fault. Using this algorithm an increase in fault coverage for a multiplier circuit from 30% to over 70% was achieved. The generality of ATSG algorithm was extended to include the generation of stimuli for static DC supply current tests using a technique analogous to the sensitive path algorithm used for automatic test pattern generation for digital circuits. The fast DC test is applied first to remove those faults that cause gross malfunction of the circuit followed by more sophisticated and expensive time domain IRMS test to detect those faults remaining.
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Published date: 1998
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Local EPrints ID: 463291
URI: http://eprints.soton.ac.uk/id/eprint/463291
PURE UUID: 3a3c46b9-f4f1-40fe-b11e-acaf9765ae36
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Date deposited: 04 Jul 2022 20:48
Last modified: 04 Jul 2022 20:48
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Author:
Christopher David Chalk
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