Inexact analogue CMOS neurons for VLSI neural network design
Inexact analogue CMOS neurons for VLSI neural network design
Artificial Neural Networks are powerful computational tools with many diverse applications in a variety of disciplines. Their implementation so far however has been mainly limited to computer simulations of their behaviour, often being too slow to realise the true potential of neural networks for real-time embedded applications. A solution to this is to make use of dedicated neural hardware, able to perform the processing at high speed and in parallel. Analogue electronic circuits provide an ideal method for achieving this, and the design, evaluation, fabrication and testing of such circuits comprises the body of this research.
The novel basis of this work, in contrast to the approach taken by most other researchers, is that simple, inaccurate neurons can be used to approximate the fundamental processes of neural computation. When combined into a full network, large scale neural functioning is maintained despite the small-scale inaccuracies at the neuron level. Compact and simple CMOS circuits are used to create the elements for analogue electronic neurons which can be interconnected to form large parallel neural network systems.
Initially considered is the design and testing of the neuron circuits, with an investigation into the immunity of neural systems to internal computation errors. Simulations are performed with SPICE and a dedicated simulator suite NEUSIM, purpose written to facilitate neural network simulations with the electronic circuits. The performance of the electronic network is compared with that of an 'ideal' mathematical neural network in several benchmark tests, and a variety of suggested uses for such a network are investigated, including printed character recognition and circuit fault diagnosis.
The design, fabrication and testing of a mixed signal VLSI prototype neural chip is also documented. The chip contains neuron circuits for operational testing and a small electronic neural network. Quantitative performance results are obtained from the chip and compared with those reported for equivalent implementations in the literature.
University of Southampton
1998
Voysey, Matthew David
(1998)
Inexact analogue CMOS neurons for VLSI neural network design.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
Artificial Neural Networks are powerful computational tools with many diverse applications in a variety of disciplines. Their implementation so far however has been mainly limited to computer simulations of their behaviour, often being too slow to realise the true potential of neural networks for real-time embedded applications. A solution to this is to make use of dedicated neural hardware, able to perform the processing at high speed and in parallel. Analogue electronic circuits provide an ideal method for achieving this, and the design, evaluation, fabrication and testing of such circuits comprises the body of this research.
The novel basis of this work, in contrast to the approach taken by most other researchers, is that simple, inaccurate neurons can be used to approximate the fundamental processes of neural computation. When combined into a full network, large scale neural functioning is maintained despite the small-scale inaccuracies at the neuron level. Compact and simple CMOS circuits are used to create the elements for analogue electronic neurons which can be interconnected to form large parallel neural network systems.
Initially considered is the design and testing of the neuron circuits, with an investigation into the immunity of neural systems to internal computation errors. Simulations are performed with SPICE and a dedicated simulator suite NEUSIM, purpose written to facilitate neural network simulations with the electronic circuits. The performance of the electronic network is compared with that of an 'ideal' mathematical neural network in several benchmark tests, and a variety of suggested uses for such a network are investigated, including printed character recognition and circuit fault diagnosis.
The design, fabrication and testing of a mixed signal VLSI prototype neural chip is also documented. The chip contains neuron circuits for operational testing and a small electronic neural network. Quantitative performance results are obtained from the chip and compared with those reported for equivalent implementations in the literature.
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Published date: 1998
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Local EPrints ID: 463365
URI: http://eprints.soton.ac.uk/id/eprint/463365
PURE UUID: 57a39001-0351-4d03-bf74-72ecc2b6e87b
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Date deposited: 04 Jul 2022 20:50
Last modified: 04 Jul 2022 20:50
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Author:
Matthew David Voysey
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