Radiation hard CMOS circuits in isolated substrate technology for analogue to digital conversion
Radiation hard CMOS circuits in isolated substrate technology for analogue to digital conversion
The application of high performance integrated circuits in military and space environments imposes a requirement to withstand the effects of exposure to ionising radiation. In such applications, dielectrically isolated CMOS technologies present significant performance advantages over other technologies by virtue of the insulated gate MOS structure, immunity to single event latch-up phenomena, and a reduced volume of active silicon for photocurrent generation. For many digital signal processing systems operating in these environments, there is the need for some radiation-tolerant analogue front-end signal interface in the form of analogue-to-digital conversion. This thesis demonstrates the application of analogue circuit design techniques for achieving high total dose radiation-hardness in analogue-to-digital converter (ADC) systems, fabricated in isolated substrate CMOS technology intended for radiation hard digital applications.
In undertaking such experimental circuit design, a stable fabrication process is important. With this in mind the GEC Plessey (now Mitel) Semiconductors (Lincoln) silicon-on-sapphire (SOS) process was used due to the availability of process data concerning both transistor parameters and radiation performance. The behavioural parallels between SOS and emerging silicon-on-insulator (SOI) processes will mean that the analysis of circuit behaviour in SOS will be mostly applicable to SOI.
This study is in several parts. Isolated substrate CMOS is examined both in terms of its particular analogue performance and in relation to radiation effects. Basic circuit cells in SOS are evaluated for floating body behaviour and radiation performance. Particular emphasis is given to the stability of the operating point with respect to bias drift at critical nodes, where small relative variations can ruin circuit functionality. Having established behavioural models from circuit level simulations, the performance of certain well-known ADC architectures are examined at system level in terms of radiation effects, to show how degradation in performance varies between architectures. As a result of these studies, two radiation hard ADCs are designed and fabricated in the 1.5μm SOS process, namely a first order switched capacitor ΣΔ modulator with 4-bit internal quantiser, and a 7-bit FLASH ADC.
University of Southampton
1998
Edwards, Christopher F
(1998)
Radiation hard CMOS circuits in isolated substrate technology for analogue to digital conversion.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
The application of high performance integrated circuits in military and space environments imposes a requirement to withstand the effects of exposure to ionising radiation. In such applications, dielectrically isolated CMOS technologies present significant performance advantages over other technologies by virtue of the insulated gate MOS structure, immunity to single event latch-up phenomena, and a reduced volume of active silicon for photocurrent generation. For many digital signal processing systems operating in these environments, there is the need for some radiation-tolerant analogue front-end signal interface in the form of analogue-to-digital conversion. This thesis demonstrates the application of analogue circuit design techniques for achieving high total dose radiation-hardness in analogue-to-digital converter (ADC) systems, fabricated in isolated substrate CMOS technology intended for radiation hard digital applications.
In undertaking such experimental circuit design, a stable fabrication process is important. With this in mind the GEC Plessey (now Mitel) Semiconductors (Lincoln) silicon-on-sapphire (SOS) process was used due to the availability of process data concerning both transistor parameters and radiation performance. The behavioural parallels between SOS and emerging silicon-on-insulator (SOI) processes will mean that the analysis of circuit behaviour in SOS will be mostly applicable to SOI.
This study is in several parts. Isolated substrate CMOS is examined both in terms of its particular analogue performance and in relation to radiation effects. Basic circuit cells in SOS are evaluated for floating body behaviour and radiation performance. Particular emphasis is given to the stability of the operating point with respect to bias drift at critical nodes, where small relative variations can ruin circuit functionality. Having established behavioural models from circuit level simulations, the performance of certain well-known ADC architectures are examined at system level in terms of radiation effects, to show how degradation in performance varies between architectures. As a result of these studies, two radiation hard ADCs are designed and fabricated in the 1.5μm SOS process, namely a first order switched capacitor ΣΔ modulator with 4-bit internal quantiser, and a 7-bit FLASH ADC.
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Published date: 1998
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Local EPrints ID: 463514
URI: http://eprints.soton.ac.uk/id/eprint/463514
PURE UUID: cef76972-08aa-4965-99ce-71565b88a87b
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Date deposited: 04 Jul 2022 20:52
Last modified: 04 Jul 2022 20:52
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Author:
Christopher F Edwards
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