Applications of Si/SiGe heterostructures to CMOS devices
Applications of Si/SiGe heterostructures to CMOS devices
For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometre regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performances or to relax the technological challenges. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics.
The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations.
The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapour deposition oxide and plasma anodic oxide. Low field mobilities, μo are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge concentrations.
University of Southampton
1999
Sidek, Roslina Mohd
(1999)
Applications of Si/SiGe heterostructures to CMOS devices.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometre regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performances or to relax the technological challenges. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics.
The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations.
The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapour deposition oxide and plasma anodic oxide. Low field mobilities, μo are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge concentrations.
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Published date: 1999
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Local EPrints ID: 463665
URI: http://eprints.soton.ac.uk/id/eprint/463665
PURE UUID: 5f4062af-9746-4348-8849-2a456f76b840
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Date deposited: 04 Jul 2022 20:55
Last modified: 04 Jul 2022 20:55
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Author:
Roslina Mohd Sidek
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