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Elevated source/drain MOSFETs for deep submicron VLSI

Elevated source/drain MOSFETs for deep submicron VLSI
Elevated source/drain MOSFETs for deep submicron VLSI

This thesis reports on the subject of elevated source/drain (ESD) MOSFETs. ESD MOSFETs are identical to conventional MOSFETs except that films selective epitaxial silicon (in which epitaxial silicon is deposited on areas of the wafer where silicon is exposed to the epitaxial silicon ambient, but not upon silicon nitride or silicon oxide) are deposited in the source and drain regions of the MOSFET after sidewall spacer creation and before HDD implantation.

This thesis describes a new process which integrates ESD MOSFETs into a 0.25 μm CMOS process. The new process uses an identical isolation scheme, well implantation, HDD/RTP, salicide and back end as a conventional CMOS process.

The new ESD MOSFET overcomes the problems associated with previously reported ESD MOSFETS. The new device described in this thesis incorporate a dual sidewall spacer scheme and are the first ESD MOSFETs to have both facet free selective epitaxial silicon and an advanced Co/Ti salicidation scheme.

Electrical characterisation of these devices show that the new NMOS ESD devices have similar electrical performance to their conventional counterparts, and that small PMOS elevated devices have considerably higher current drive and less susceptibility to the short channel effect than their environmental counterparts. Electrical characterisation of these devices shows that the elevated structure reduces the source/drain series resistance of the PMOS ESD devices.

Good yield and circuit performance of the devices is demonstrated by the first ring oscillators to be fabricated with NMOS and PMOS ESD MOSFETs. Ring oscillators fabricated with the new ESD MOSFETs are 20% faster than ring oscillators fabricated with conventional devices.

TCAD technology simulation of the new devices shows that the reduction in the short channel effect is caused by the elevated source/drain structures acting as sinks for boron atoms from the LDD and HDD implants. The sinks suppress boron diffusion into the channel of the device improving short channel performance. TCAD simulations are also used to investigate the properties of the new device architecture further.

University of Southampton
Waite, Andrew Michael
Waite, Andrew Michael

Waite, Andrew Michael (1999) Elevated source/drain MOSFETs for deep submicron VLSI. University of Southampton, Doctoral Thesis.

Record type: Thesis (Doctoral)

Abstract

This thesis reports on the subject of elevated source/drain (ESD) MOSFETs. ESD MOSFETs are identical to conventional MOSFETs except that films selective epitaxial silicon (in which epitaxial silicon is deposited on areas of the wafer where silicon is exposed to the epitaxial silicon ambient, but not upon silicon nitride or silicon oxide) are deposited in the source and drain regions of the MOSFET after sidewall spacer creation and before HDD implantation.

This thesis describes a new process which integrates ESD MOSFETs into a 0.25 μm CMOS process. The new process uses an identical isolation scheme, well implantation, HDD/RTP, salicide and back end as a conventional CMOS process.

The new ESD MOSFET overcomes the problems associated with previously reported ESD MOSFETS. The new device described in this thesis incorporate a dual sidewall spacer scheme and are the first ESD MOSFETs to have both facet free selective epitaxial silicon and an advanced Co/Ti salicidation scheme.

Electrical characterisation of these devices show that the new NMOS ESD devices have similar electrical performance to their conventional counterparts, and that small PMOS elevated devices have considerably higher current drive and less susceptibility to the short channel effect than their environmental counterparts. Electrical characterisation of these devices shows that the elevated structure reduces the source/drain series resistance of the PMOS ESD devices.

Good yield and circuit performance of the devices is demonstrated by the first ring oscillators to be fabricated with NMOS and PMOS ESD MOSFETs. Ring oscillators fabricated with the new ESD MOSFETs are 20% faster than ring oscillators fabricated with conventional devices.

TCAD technology simulation of the new devices shows that the reduction in the short channel effect is caused by the elevated source/drain structures acting as sinks for boron atoms from the LDD and HDD implants. The sinks suppress boron diffusion into the channel of the device improving short channel performance. TCAD simulations are also used to investigate the properties of the new device architecture further.

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Published date: 1999

Identifiers

Local EPrints ID: 463914
URI: http://eprints.soton.ac.uk/id/eprint/463914
PURE UUID: 46b7ddde-a6d3-4e55-b41a-ce124c2d9de3

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Date deposited: 04 Jul 2022 20:58
Last modified: 04 Jul 2022 20:58

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Author: Andrew Michael Waite

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