Asynchronous and multiple clock domain synthesis for large scale systems
Asynchronous and multiple clock domain synthesis for large scale systems
The MOODS (Multiple Objective Optimisation for Data and control path Synthesis) behavioural synthesis tool has been developed at the University of Southampton over the last 15 years. Behavioural synthesis is the process of transforming an algorithmic specification into a structural netlist. By designing digital systems at this higher level of abstraction the designer can concentrate on high level decisions, as opposed to the details of the low level logic. The original MOODS system synthesised synchronous circuits using a single clock source, however the assumption that a clock remains synchronous over the entire silicon area is becoming less valid as chip sizes and clock speeds increase. This thesis describes how the system has been modified (in two different ways) to facilitate the design of larger systems by incorporating capabilities to overcome these difficulties.
The first technique presented in the synthesis of asynchronous circuits. Asynchronous circuits do not use a clock and therefore do not suffer from the clock skew that causes problems for synchronous circuit designers. Asynchronous circuits do not require a fixed length clock cycle, using local handshaking instead and the examples presented in this thesis have on average 57% of the latency (the time between an input event and its corresponding output event) of their synchronous equivalent circuits for data intensive applications.
The second approach describes the synthesis of systems with more than one clock domain (Islands of Synchronicity); the circuit is partitioned into many clock domains each at a different frequency or phase to the others. These domains communicate through asynchronous channels to guarantee secure data transfer. They have also been shown to have the same latency reduction as the previous technique and require only 90% of the area.
Finally the design of two systems using the concepts of multiple clock domains and channels are presented. The first is the design and construction of an audio encryption system with visualisation and the second is the synthesis of the ES (Rijndael) algorithm using channels to create a fast, pipelined design.
University of Southampton
Sacker, Matthew
284de2af-dbcd-4257-a35b-b6fbb7c2a7e4
2005
Sacker, Matthew
284de2af-dbcd-4257-a35b-b6fbb7c2a7e4
Sacker, Matthew
(2005)
Asynchronous and multiple clock domain synthesis for large scale systems.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
The MOODS (Multiple Objective Optimisation for Data and control path Synthesis) behavioural synthesis tool has been developed at the University of Southampton over the last 15 years. Behavioural synthesis is the process of transforming an algorithmic specification into a structural netlist. By designing digital systems at this higher level of abstraction the designer can concentrate on high level decisions, as opposed to the details of the low level logic. The original MOODS system synthesised synchronous circuits using a single clock source, however the assumption that a clock remains synchronous over the entire silicon area is becoming less valid as chip sizes and clock speeds increase. This thesis describes how the system has been modified (in two different ways) to facilitate the design of larger systems by incorporating capabilities to overcome these difficulties.
The first technique presented in the synthesis of asynchronous circuits. Asynchronous circuits do not use a clock and therefore do not suffer from the clock skew that causes problems for synchronous circuit designers. Asynchronous circuits do not require a fixed length clock cycle, using local handshaking instead and the examples presented in this thesis have on average 57% of the latency (the time between an input event and its corresponding output event) of their synchronous equivalent circuits for data intensive applications.
The second approach describes the synthesis of systems with more than one clock domain (Islands of Synchronicity); the circuit is partitioned into many clock domains each at a different frequency or phase to the others. These domains communicate through asynchronous channels to guarantee secure data transfer. They have also been shown to have the same latency reduction as the previous technique and require only 90% of the area.
Finally the design of two systems using the concepts of multiple clock domains and channels are presented. The first is the design and construction of an audio encryption system with visualisation and the second is the synthesis of the ES (Rijndael) algorithm using channels to create a fast, pipelined design.
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Published date: 2005
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Local EPrints ID: 465684
URI: http://eprints.soton.ac.uk/id/eprint/465684
PURE UUID: 5b14dec0-2aa1-46c9-a808-2523866d245a
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Date deposited: 05 Jul 2022 02:34
Last modified: 05 Jul 2022 02:34
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Author:
Matthew Sacker
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