Topologies for programmable analogue circuits

Abstract

Modern VLSI design has always tried to shorten the design cycles for digital and analogue circuits. This effort has been very successful over the past years for digital integrated circuits, through the development of FPGAs (Field Programmable Gate Arrays) and appropriate CAD methodologies to suit the design flow. Although a very low paced development, for the analogue circuits due to complexities in the analogue domain, the role of Field Programmable Analogue Arrays (FPAAs) to enable rapid prototyping and testability of an analogue design solution has been realised by the industry. Hence, different types of programmable analogue circuits, have been developed to suit specific applications. But none of these FPAAs have actually addressed the problems of choosing an appropriate analogue building block, an architecture and the routing strategies between them. Hence, this research focuses on the "Topologies for Programmable Analogue Circuits" and also in the development of a target FPAA chip primarily for Instrumentation and Data Acquisition Systems.

This thesis, reviews previously developed FPAAs and also summarises the key strategies for choosing a Configurable Analogue Block (CAB) and the architecture for the target FPAA. This document includes the conceptual design and tests for the chosen CAB called the Differential Difference Amplifier (DDA) integrated with the second generation Current Conveyor (CCII), to form the hybrid DDACCII CAB. The implementation of a cluster based hierarchical architecture, following a similar concept to the HFPGAs (Hierarchical Field Programmable Gate Arrays), for connecting the CABs in the target FPAA, is also included in this thesis. This thesis covers the design and fabrication of an FPAA prototype and the decisions and design trade-offs made. A methodology for interconnectivity analysis and establishing relationship between the routability of the FPAA and the flexibility if its hierarchical interconnection structures, not relying on the quality of partitioning/routing algorithms as in digital circuits, is also discussed in this thesis.

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