Design and fabrication of lateral silicon germanium heterojunction bipolar transistors

Abstract

This work provides a detailed study of device structures and fabrication routes required for the realisation of lateral SiGe heterojunction bipolar transistors (HBTs). After a comprehensive study of BJT and HBT device technologies our own designs of lateral SiGe HBT are introduced. The first design investigated is a device proposed in earlier work that utilises "SOI cavities" and confined selective epitaxial growth. Process and device characteristic simulations were performed for devices of modest lithographic mode and thick SOI suggested the device would be reach typical SiGe HBT performance levels with a cut off frequency (/r) of 15-22GHz, common emitter gain of 58-92 and maximum oscillation frequency (fmax) of 14GHz. The fabrication of the types of lateral HBT that been have explored require detailed understanding and control of selective epitaxial growth and etching techniques and each of these two important processes have been developed. Selective epitaxy growths on different crystallographic planes and seed window alignments have been carried out, and, as would be expected, selective epitaxial growth rate are seen to vary for each crystal plane. These different growth rates leads to different facet formations on lateral growth fronts that can inhibit lateral growth rates and thereby prevent the formation of suitable structures for HBT design. A mathematical model is developed that enables a prediction of these growth phenomenon. The epitaxial studies suggest that smooth vertical {100} sidewalls are required to enable suitable lateral growth two different approaches to achieve this are detailed. The first process uses conventional anisotropic plasma etching to establish followed by wet etching (KOH) for smoothing, the second technique is based on KOH etching alone. Both methods demonstrate smooth sidewalls suitable for epitaxy and the simplicity of the process that uses only KOH etching is therefore preferable. As with epitaxial growth, KOH etch rates are strongly dependent upon crystal plane a model is developed to allow an understanding of the different etch rates and facet formation. The epitaxy and etching development studies have allowed us to propose a new design of lateral SiGe HBT. Based on non-selective growth on SOI sidewalls. Simulations of this new design indicate high-speed performance with/r //max of 395/983GHz and 1.58ps ECL delay time on the 0.13mm lithographic node at collector currents of ~8mA and a common emitter gain around 600. Our results indicate great potential for such a device but highlight several fabrication challenges that requires further development before such devices can be realised.

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