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A hardware/application overlay model for large-scale neuromorphic simulation

A hardware/application overlay model for large-scale neuromorphic simulation
A hardware/application overlay model for large-scale neuromorphic simulation
Neuromorphic computing is gaining momentum as an alternative hardware platform for large-scale neural simulation. However, with several major devices and systems available and planned, often with very different characteristics, it is not always clear which platform is suitable for which application. Simulating the platform on conventional computers is typically too slow to be of use, but an alternative approach is to implement an `emulation' of the hardware in FPGAs which can execute at near-hardware speeds but does not commit to a specific hardware architecture. We present an overlay model - a method which superimposes bespoke features on top of a standard template - in both hardware and software to implement neuromorphic architectures using the POETS (Partially Ordered Event Triggered Systems) system. This combination of overlays permits very large-scale simulations to be performed in real time for hardware exploration or application verification, while retaining the flexibility to redefine either the hardware or software layer, if results indicate potential to improve performance, or significant design problems. Using this system we simulate up to 500,000 neurons on a single-box system, that can be scaled to ~4,000,000 neurons in an 8-box configuration. Results indicate the crucial constraint for real-time simulation: peak input spike rate per neuron; and help to optimise both hardware and software around neural application requirements. The preliminary architecture demonstrates the feasibility of an overlay model, while indicating directions for future neuromorphic systems. With POETS, we introduce a platform that can help to shape and investigate the neuromorphic architectures of the future.
IEEE
Rast, Alexander
2f3b577b-40b9-46d4-887b-56c53a8e13f5
Shahsavari, Mahyar
a120fae7-9361-4f5d-ad6a-60f50f84da34
Bragg, Graeme M
b5fd19b9-1a51-470b-a226-2d4dd5ff447a
Vousden, Mark L
72f20dc7-d350-4982-a680-2d1f9ed5f07f
Thomas, David
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Rast, Alexander
2f3b577b-40b9-46d4-887b-56c53a8e13f5
Shahsavari, Mahyar
a120fae7-9361-4f5d-ad6a-60f50f84da34
Bragg, Graeme M
b5fd19b9-1a51-470b-a226-2d4dd5ff447a
Vousden, Mark L
72f20dc7-d350-4982-a680-2d1f9ed5f07f
Thomas, David
5701997d-7de3-4e57-a802-ea2bd3e6ab6c
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0

Rast, Alexander, Shahsavari, Mahyar, Bragg, Graeme M, Vousden, Mark L, Thomas, David and Brown, Andrew (2020) A hardware/application overlay model for large-scale neuromorphic simulation. In 2020 International Joint Conference on Neural Networks (IJCNN). IEEE. 9 pp . (doi:10.1109/IJCNN48605.2020.9206708).

Record type: Conference or Workshop Item (Paper)

Abstract

Neuromorphic computing is gaining momentum as an alternative hardware platform for large-scale neural simulation. However, with several major devices and systems available and planned, often with very different characteristics, it is not always clear which platform is suitable for which application. Simulating the platform on conventional computers is typically too slow to be of use, but an alternative approach is to implement an `emulation' of the hardware in FPGAs which can execute at near-hardware speeds but does not commit to a specific hardware architecture. We present an overlay model - a method which superimposes bespoke features on top of a standard template - in both hardware and software to implement neuromorphic architectures using the POETS (Partially Ordered Event Triggered Systems) system. This combination of overlays permits very large-scale simulations to be performed in real time for hardware exploration or application verification, while retaining the flexibility to redefine either the hardware or software layer, if results indicate potential to improve performance, or significant design problems. Using this system we simulate up to 500,000 neurons on a single-box system, that can be scaled to ~4,000,000 neurons in an 8-box configuration. Results indicate the crucial constraint for real-time simulation: peak input spike rate per neuron; and help to optimise both hardware and software around neural application requirements. The preliminary architecture demonstrates the feasibility of an overlay model, while indicating directions for future neuromorphic systems. With POETS, we introduce a platform that can help to shape and investigate the neuromorphic architectures of the future.

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More information

e-pub ahead of print date: 28 August 2020
Venue - Dates: 2020 International Joint Conference on Neural Networks, , Glasgow, United Kingdom, 2020-07-19 - 2020-07-24

Identifiers

Local EPrints ID: 470107
URI: http://eprints.soton.ac.uk/id/eprint/470107
PURE UUID: 716120d3-48c1-401b-8c0d-f913e75fc526
ORCID for Graeme M Bragg: ORCID iD orcid.org/0000-0002-5201-7977
ORCID for David Thomas: ORCID iD orcid.org/0000-0002-9671-0917

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Date deposited: 03 Oct 2022 16:52
Last modified: 17 Mar 2024 04:10

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Contributors

Author: Alexander Rast
Author: Mahyar Shahsavari
Author: Graeme M Bragg ORCID iD
Author: Mark L Vousden
Author: David Thomas ORCID iD
Author: Andrew Brown

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