Using formal methods to evaluate hardware reliability in the presence of soft errors
Using formal methods to evaluate hardware reliability in the presence of soft errors
Reliability is a major concern in many embedded systems. Redundancy-based methods are widely used against Single Event Upsets, causing significant temporal and spatial overhead. The traditional method to evaluate the reliability of a system is fault injection. However, it is practically impossible to test all faults for a complex design due to intractable simulation times. In this paper, we propose using formal methods to evaluate hardware reliability in the presence of soft errors. The proposed method can exhaustively search the entire state space and the whole fault list in a reasonable time. The method is applied to assess the vulnerability of all registers in a RISC-V Ibex core.
fault injection, Formal verification, hardware reliability, single event upset, soft errors
29-32
Xue, Bing
755777ee-472d-49a9-8cec-f6866530778c
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
11 June 2022
Xue, Bing
755777ee-472d-49a9-8cec-f6866530778c
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Xue, Bing and Zwolinski, Mark
(2022)
Using formal methods to evaluate hardware reliability in the presence of soft errors.
In PRIME 2022 - 17th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings.
IEEE.
.
(doi:10.1109/PRIME55000.2022.9816775).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Reliability is a major concern in many embedded systems. Redundancy-based methods are widely used against Single Event Upsets, causing significant temporal and spatial overhead. The traditional method to evaluate the reliability of a system is fault injection. However, it is practically impossible to test all faults for a complex design due to intractable simulation times. In this paper, we propose using formal methods to evaluate hardware reliability in the presence of soft errors. The proposed method can exhaustively search the entire state space and the whole fault list in a reasonable time. The method is applied to assess the vulnerability of all registers in a RISC-V Ibex core.
This record has no associated files available for download.
More information
Published date: 11 June 2022
Additional Information:
Publisher Copyright:
© 2022 IEEE.
Venue - Dates:
17th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2022, , Villasimius, Italy, 2022-06-12 - 2022-06-15
Keywords:
fault injection, Formal verification, hardware reliability, single event upset, soft errors
Identifiers
Local EPrints ID: 472220
URI: http://eprints.soton.ac.uk/id/eprint/472220
PURE UUID: f40f83a5-ba56-4da3-97c9-cd363b57b690
Catalogue record
Date deposited: 29 Nov 2022 17:50
Last modified: 17 Mar 2024 02:35
Export record
Altmetrics
Contributors
Author:
Bing Xue
Author:
Mark Zwolinski
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics