Survey of Lockstep based Mitigation Techniques for Soft Errors in Embedded Systems
Survey of Lockstep based Mitigation Techniques for Soft Errors in Embedded Systems
Soft errors are one of the significant design technology challenges at smaller technology nodes and especially in radiation enviro nments. This paper presents a particular class of approaches to provide reliability against radiation-induced soft errors. The paper provides a review of the lockstep mechanism across different levels of design abstraction: processor design, architectural level, and the software level. This work explores techniques providing modifications in the processor pipeline, techniques allied with FPGA dynamic reconfiguration strategies and different types of spatial redundancy.
Lockstep, Reliability, Fault Tolerance, soft error mitigation, radiation effects
124-127
Wachter, Eduardo Weber
bdacc537-b1ac-4241-a6fc-b67f1e6a6ce8
Kasap, Server
e49310e0-96aa-42e1-8259-6ad34cc1b025
Zhai, Xiaojun
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Ehsan, Shoaib
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McDonald-Maier, Klaus
4429a771-384b-4cc6-8d45-1813c3792939
20 September 2019
Wachter, Eduardo Weber
bdacc537-b1ac-4241-a6fc-b67f1e6a6ce8
Kasap, Server
e49310e0-96aa-42e1-8259-6ad34cc1b025
Zhai, Xiaojun
93ee3dbb-e10e-472b-adec-78acfcd4cbc7
Ehsan, Shoaib
ae8922f0-dbe0-4b22-8474-98e84d852de7
McDonald-Maier, Klaus
4429a771-384b-4cc6-8d45-1813c3792939
Wachter, Eduardo Weber, Kasap, Server, Zhai, Xiaojun, Ehsan, Shoaib and McDonald-Maier, Klaus
(2019)
Survey of Lockstep based Mitigation Techniques for Soft Errors in Embedded Systems.
In 2019 11th Computer Science and Electronic Engineering (CEEC).
IEEE.
.
(doi:10.1109/CEEC47804.2019.8974333).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Soft errors are one of the significant design technology challenges at smaller technology nodes and especially in radiation enviro nments. This paper presents a particular class of approaches to provide reliability against radiation-induced soft errors. The paper provides a review of the lockstep mechanism across different levels of design abstraction: processor design, architectural level, and the software level. This work explores techniques providing modifications in the processor pipeline, techniques allied with FPGA dynamic reconfiguration strategies and different types of spatial redundancy.
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Published date: 20 September 2019
Venue - Dates:
2019 11th Computer Science and Electronic Engineering (CEEC), , Colchester, United Kingdom, 2019-09-18 - 2019-09-20
Keywords:
Lockstep, Reliability, Fault Tolerance, soft error mitigation, radiation effects
Identifiers
Local EPrints ID: 472626
URI: http://eprints.soton.ac.uk/id/eprint/472626
ISSN: 2472-1530
PURE UUID: bf393a55-9802-4956-a1cf-a5420a3f3b1f
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Date deposited: 12 Dec 2022 17:51
Last modified: 17 Mar 2024 04:16
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Contributors
Author:
Eduardo Weber Wachter
Author:
Server Kasap
Author:
Xiaojun Zhai
Author:
Shoaib Ehsan
Author:
Klaus McDonald-Maier
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