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A cost-efficient aging sensor based on multiple paths delay fault monitoring

A cost-efficient aging sensor based on multiple paths delay fault monitoring
A cost-efficient aging sensor based on multiple paths delay fault monitoring
Aggressive technology shrinking has increased the sensitivity of integrated circuits in terms of devices ageing. As a result, the performance of a CMOS device will degrade significantly over time and, therefore, results in the delay faults. In situ delay fault monitoring schemes have been proposed to ensure the reliability of an IC during its lifetime. Such schemes are usually based on the application of ageing sensors to predict ageing-induced failures of a circuit and react accordingly. Traditional ageing sensors are implemented on the near-critical paths, which are considered as the most vulnerable paths to delay faults caused by performance degradation. However, today’s complex designs and technology node shrinking have enhanced the number of near- and potential critical paths that need to be monitored. This means the in situ delay fault monitoring approaches are becoming very expensive and may be infeasible. This chapter introduces a state-of-the-art in situ delay monitor called Differential Multiple Error Detection Sensor (DMEDS). The chapter presents a case study to demonstrate how the DMEDS monitors multiple paths simultaneously, and it discusses the advantages and disadvantages of this proposed approach compared with the traditional techniques.
211-223
Springer
Sai, Gaole
6fc26dc4-af9d-4409-9de4-7b639846da85
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Halak, Basel
Sai, Gaole
6fc26dc4-af9d-4409-9de4-7b639846da85
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Halak, Basel

Sai, Gaole, Zwolinski, Mark and Halak, Basel (2019) A cost-efficient aging sensor based on multiple paths delay fault monitoring. In, Halak, Basel (ed.) Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques. Springer, pp. 211-223. (doi:10.1007/978-3-030-23781-3_8).

Record type: Book Section

Abstract

Aggressive technology shrinking has increased the sensitivity of integrated circuits in terms of devices ageing. As a result, the performance of a CMOS device will degrade significantly over time and, therefore, results in the delay faults. In situ delay fault monitoring schemes have been proposed to ensure the reliability of an IC during its lifetime. Such schemes are usually based on the application of ageing sensors to predict ageing-induced failures of a circuit and react accordingly. Traditional ageing sensors are implemented on the near-critical paths, which are considered as the most vulnerable paths to delay faults caused by performance degradation. However, today’s complex designs and technology node shrinking have enhanced the number of near- and potential critical paths that need to be monitored. This means the in situ delay fault monitoring approaches are becoming very expensive and may be infeasible. This chapter introduces a state-of-the-art in situ delay monitor called Differential Multiple Error Detection Sensor (DMEDS). The chapter presents a case study to demonstrate how the DMEDS monitors multiple paths simultaneously, and it discusses the advantages and disadvantages of this proposed approach compared with the traditional techniques.

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Published date: 1 October 2019

Identifiers

Local EPrints ID: 473036
URI: http://eprints.soton.ac.uk/id/eprint/473036
PURE UUID: 5a19085e-cf55-4df5-8ef8-72faeeb6e87b
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

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Date deposited: 09 Jan 2023 18:22
Last modified: 06 Jun 2024 01:49

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Contributors

Author: Gaole Sai
Author: Mark Zwolinski ORCID iD
Author: Basel Halak ORCID iD
Editor: Basel Halak

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