Duan, Shengyu, Zwolinski, Mark and Halak, Basel (2019) Ageing-aware logic synthesis. In, Halak, Basel (ed.) Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques. Springer, pp. 113-145. (doi:10.1007/978-3-030-23781-3_5).
Abstract
CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.
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