The University of Southampton
University of Southampton Institutional Repository

Ageing-aware logic synthesis

Ageing-aware logic synthesis
Ageing-aware logic synthesis
CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.
113-145
Springer
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Halak, Basel
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Halak, Basel

Duan, Shengyu, Zwolinski, Mark and Halak, Basel (2019) Ageing-aware logic synthesis. In, Halak, Basel (ed.) Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques. Springer, pp. 113-145. (doi:10.1007/978-3-030-23781-3_5).

Record type: Book Section

Abstract

CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.

This record has no associated files available for download.

More information

Published date: 1 October 2019

Identifiers

Local EPrints ID: 473037
URI: http://eprints.soton.ac.uk/id/eprint/473037
PURE UUID: 2dc81600-7e70-43d3-b3e1-35f3152e4989
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 09 Jan 2023 18:22
Last modified: 06 Jun 2024 01:49

Export record

Altmetrics

Contributors

Author: Shengyu Duan
Author: Mark Zwolinski ORCID iD
Author: Basel Halak ORCID iD
Editor: Basel Halak

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×