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Aging mitigation techniques for microprocessors using anti-aging software

Aging mitigation techniques for microprocessors using anti-aging software
Aging mitigation techniques for microprocessors using anti-aging software
In this chapter, we will aim to reverse the aging stress on the functional units of the processor by applying high-level workloads as anti-aging patterns into the stressed component. We present a time-redundant technique to mitigate negative and positive bias temperature instability (NBTI/PBTI) aging effects on the combinational units of a processor. We have analysed the sources and effects of aging from the device level to the instruction set architecture (ISA) level and have found that an application may stress the critical paths in such a way that the combinational circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be extended by applying balanced stress patterns at a higher level of abstraction and during the idle time of a processor system.
67-89
Springer
Abbas, Haider Muhi
df25f48a-4b00-4913-8456-d80a0c31ac10
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Halak, Bsel
Abbas, Haider Muhi
df25f48a-4b00-4913-8456-d80a0c31ac10
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Halak, Bsel

Abbas, Haider Muhi, Zwolinski, Mark and Halak, Basel (2019) Aging mitigation techniques for microprocessors using anti-aging software. In, Halak, Bsel (ed.) Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques. Springer, pp. 67-89. (doi:10.1007/978-3-030-23781-3_3).

Record type: Book Section

Abstract

In this chapter, we will aim to reverse the aging stress on the functional units of the processor by applying high-level workloads as anti-aging patterns into the stressed component. We present a time-redundant technique to mitigate negative and positive bias temperature instability (NBTI/PBTI) aging effects on the combinational units of a processor. We have analysed the sources and effects of aging from the device level to the instruction set architecture (ISA) level and have found that an application may stress the critical paths in such a way that the combinational circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be extended by applying balanced stress patterns at a higher level of abstraction and during the idle time of a processor system.

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More information

Published date: 1 October 2019

Identifiers

Local EPrints ID: 473042
URI: http://eprints.soton.ac.uk/id/eprint/473042
PURE UUID: e4b4d957-334f-4f45-a2f2-b7d6b434dc5f
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

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Date deposited: 09 Jan 2023 18:23
Last modified: 06 Jun 2024 01:49

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Contributors

Author: Haider Muhi Abbas
Author: Mark Zwolinski ORCID iD
Author: Basel Halak ORCID iD
Editor: Bsel Halak

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