Dataset supporting publication "Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs"
Dataset supporting publication "Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs"
This dataset supports the publication " Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs " to be published in the Proceedings of the 2023 Design, Automation and Test in Europe Conference and Exhibition.
This dataset contains: - 'Fig2a.csv': Data supporting Fig. 2 (a). Execution time in ms of the Dynamic Deep Neural Network on different platforms. (CPU, CPU+GPU, Jetson Xavier and FPGA Xilinx ZCU106). - 'Fig2b.csv': Data supporting Fig. 2 (b). Energy consumption and needed power for the execution of the Dynamic Deep Neural network on different platforms. (CPU, CPU+GPU, Jetson Xavier and FPGA Xilinx ZCU106).
Related projects: Engineering and Physical Sciences Research Council (EPSRC) under EP/S030069/1
Licence: CC BY 4.0
University of Southampton
Dimitriou, Anastasios
02f87799-17dc-4271-96c3-8b30e64e659e
Hu, Mingyu
686551f3-f76b-471d-b424-71a5c68851da
Hare, Jonathon
65ba2cda-eaaf-4767-a325-cd845504e5a9
Merrett, Geoffrey
89b3a696-41de-44c3-89aa-b0aa29f54020
Dimitriou, Anastasios
02f87799-17dc-4271-96c3-8b30e64e659e
Hu, Mingyu
686551f3-f76b-471d-b424-71a5c68851da
Hare, Jonathon
65ba2cda-eaaf-4767-a325-cd845504e5a9
Merrett, Geoffrey
89b3a696-41de-44c3-89aa-b0aa29f54020
Dimitriou, Anastasios
(2023)
Dataset supporting publication "Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs".
University of Southampton
doi:10.5258/SOTON/D2514
[Dataset]
Abstract
This dataset supports the publication " Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs " to be published in the Proceedings of the 2023 Design, Automation and Test in Europe Conference and Exhibition.
This dataset contains: - 'Fig2a.csv': Data supporting Fig. 2 (a). Execution time in ms of the Dynamic Deep Neural Network on different platforms. (CPU, CPU+GPU, Jetson Xavier and FPGA Xilinx ZCU106). - 'Fig2b.csv': Data supporting Fig. 2 (b). Energy consumption and needed power for the execution of the Dynamic Deep Neural network on different platforms. (CPU, CPU+GPU, Jetson Xavier and FPGA Xilinx ZCU106).
Related projects: Engineering and Physical Sciences Research Council (EPSRC) under EP/S030069/1
Licence: CC BY 4.0
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Published date: 19 April 2023
Identifiers
Local EPrints ID: 473764
URI: http://eprints.soton.ac.uk/id/eprint/473764
PURE UUID: a95a5fa7-464f-41c8-abfe-cd81046be3be
Catalogue record
Date deposited: 31 Jan 2023 17:39
Last modified: 06 May 2023 01:41
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Contributors
Creator:
Anastasios Dimitriou
Contributor:
Mingyu Hu
Research team head:
Jonathon Hare
Research team head:
Geoffrey Merrett
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